Simulation Results: lc_ctrl/volatile_unlock_enabled

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.69 %
  • code
  • 84.57 %
  • assert
  • 94.97 %
  • func
  • 92.53 %
  • line
  • 97.13 %
  • branch
  • 93.66 %
  • cond
  • 79.27 %
  • toggle
  • 88.31 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.570s 103.222us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.760s 19.146us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.990s 66.756us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.190s 119.574us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 109.288us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.120s 22.676us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.990s 66.756us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 109.288us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.160s 413.983us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.170s 492.843us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.980s 17.711us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.970s 77.951us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.850s 446.000us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.840s 316.136us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.850s 446.000us 1 1 100.00
lc_ctrl_prog_failure 1.970s 77.951us 1 1 100.00
lc_ctrl_errors 6.840s 316.136us 1 1 100.00
lc_ctrl_security_escalation 5.640s 3445.993us 1 1 100.00
lc_ctrl_jtag_state_failure 18.030s 1319.948us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.390s 1133.714us 1 1 100.00
lc_ctrl_jtag_errors 20.710s 4203.161us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.870s 2127.611us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.130s 906.133us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.390s 1133.714us 1 1 100.00
lc_ctrl_jtag_errors 20.710s 4203.161us 1 1 100.00
lc_ctrl_jtag_access 4.200s 294.590us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.310s 999.194us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.010s 151.192us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.300s 193.094us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 18.410s 3450.277us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.400s 1554.591us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.250s 56.534us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.880s 257.234us 1 1 100.00
lc_ctrl_jtag_alert_test 1.590s 170.248us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.160s 170.372us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.180s 16.440us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 35.950s 2904.082us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.060s 179.613us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.470s 113.717us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.470s 113.717us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 19.146us 1 1 100.00
lc_ctrl_csr_rw 0.990s 66.756us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 109.288us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.330s 51.021us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 19.146us 1 1 100.00
lc_ctrl_csr_rw 0.990s 66.756us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 109.288us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.330s 51.021us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.160s 841.382us 1 1 100.00
lc_ctrl_tl_intg_err 1.810s 340.422us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.810s 340.422us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.170s 492.843us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.850s 446.000us 1 1 100.00
lc_ctrl_sec_cm 6.160s 841.382us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.850s 446.000us 1 1 100.00
lc_ctrl_sec_cm 6.160s 841.382us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.850s 446.000us 1 1 100.00
lc_ctrl_sec_cm 6.160s 841.382us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.850s 446.000us 1 1 100.00
lc_ctrl_sec_cm 6.160s 841.382us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.850s 446.000us 1 1 100.00
lc_ctrl_sec_cm 6.160s 841.382us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.850s 446.000us 1 1 100.00
lc_ctrl_sec_cm 6.160s 841.382us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.850s 446.000us 1 1 100.00
lc_ctrl_sec_cm 6.160s 841.382us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.850s 446.000us 1 1 100.00
lc_ctrl_sec_cm 6.160s 841.382us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.640s 3445.993us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.160s 413.983us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.130s 906.133us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.490s 452.281us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.490s 452.281us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.560s 289.846us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.090s 417.492us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.090s 417.492us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 36.180s 3112.829us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 47254918326782791764239298920547630810636176917975440004293038236340286826934 4119
UVM_INFO @ 3112829479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---