Simulation Results: otbn

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.21 %
  • code
  • 95.28 %
  • assert
  • 90.33 %
  • func
  • 97.03 %
  • block
  • 99.39 %
  • line
  • 99.54 %
  • branch
  • 92.40 %
  • toggle
  • 91.61 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 44.077us 1 1 100.00
single_binary 1 1 100.00
otbn_single 8.000s 54.865us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 111.110us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 35.292us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 9.000s 618.144us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 7.000s 50.831us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 24.002us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 35.292us 1 1 100.00
otbn_csr_aliasing 7.000s 50.831us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 65.000s 11904.392us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 38.000s 1138.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 31.000s 385.892us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 49.000s 710.155us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 30.000s 90.750us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 68.000s 1001.215us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 27.067us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 11.377us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 38.058us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 9.000s 69.932us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 27.585us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 40.217us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 40.217us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 111.110us 1 1 100.00
otbn_csr_rw 3.000s 35.292us 1 1 100.00
otbn_csr_aliasing 7.000s 50.831us 1 1 100.00
otbn_same_csr_outstanding 5.000s 26.026us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 111.110us 1 1 100.00
otbn_csr_rw 3.000s 35.292us 1 1 100.00
otbn_csr_aliasing 7.000s 50.831us 1 1 100.00
otbn_same_csr_outstanding 5.000s 26.026us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 129.408us 1 1 100.00
otbn_dmem_err 7.000s 35.709us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 13.000s 66.728us 1 1 100.00
otbn_controller_ispr_rdata_err 12.000s 65.208us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 61.985us 1 1 100.00
otbn_urnd_err 5.000s 39.503us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.696us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 75.011us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 45.867us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
otbn_tl_intg_err 10.000s 125.948us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 51.000s 264.144us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 44.077us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 35.709us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 129.408us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 125.948us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 27.067us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 129.408us 1 1 100.00
otbn_dmem_err 7.000s 35.709us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 11.377us 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.696us 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 8.000s 54.865us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 129.408us 1 1 100.00
otbn_dmem_err 7.000s 35.709us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 11.377us 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.696us 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 27.067us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 129.408us 1 1 100.00
otbn_dmem_err 7.000s 35.709us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 11.377us 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.696us 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 8.000s 54.865us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 13.137us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 16.783us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 27.000s 197.656us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 27.000s 197.656us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 28.419us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 0 1 0.00
otbn_rf_bignum_intg_err 7.000s 33.468us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 14.463us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 14.463us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 10.238us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 54.865us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 54.865us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 8.000s 54.865us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 30.000s 90.750us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 8.000s 54.865us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 8.000s 54.865us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 101.535us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 8.000s 54.865us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 419.000s 2646.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 9.000s 431.931us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 84.775us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_rf_bignum_intg_err 100138550284517316097299263391573962405622461620784199386566845225840896823185 109
UVM_INFO @ 33467554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 98497811446219031648290394425615310520832696056432435331257392514345608104660 146
UVM_INFO @ 431931072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 75722837813748040476072301513046319978466383110742726900286625627852069801995 116
UVM_ERROR @ 14463003 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 14463003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---