Simulation Results: otp_ctrl

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.29 %
  • code
  • 77.82 %
  • assert
  • 94.82 %
  • func
  • 71.24 %
  • line
  • 88.54 %
  • branch
  • 83.36 %
  • cond
  • 90.24 %
  • toggle
  • 83.36 %
  • FSM
  • 43.58 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.500s 103.054us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 8.210s 1662.742us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.810s 397.466us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.630s 174.907us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.550s 1051.862us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.500s 360.295us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.490s 106.279us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.630s 174.907us 1 1 100.00
otp_ctrl_csr_aliasing 4.500s 360.295us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.720s 531.683us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.610s 560.569us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.100s 2456.337us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.880s 419.117us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 19.480s 1873.838us 1 1 100.00
otp_ctrl_check_fail 13.460s 1810.055us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.580s 536.688us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 7.820s 606.783us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 14.380s 521.523us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 11.600s 1128.014us 1 1 100.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.900s 392.750us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.580s 760.149us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 32.250s 23760.003us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 26.340s 1992.731us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.260s 75.266us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.560s 276.003us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.220s 160.877us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.220s 160.877us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.810s 397.466us 1 1 100.00
otp_ctrl_csr_rw 1.630s 174.907us 1 1 100.00
otp_ctrl_csr_aliasing 4.500s 360.295us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.480s 118.098us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.810s 397.466us 1 1 100.00
otp_ctrl_csr_rw 1.630s 174.907us 1 1 100.00
otp_ctrl_csr_aliasing 4.500s 360.295us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.480s 118.098us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
otp_ctrl_tl_intg_err 6.870s 758.353us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 6.870s 758.353us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 8.210s 1662.742us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 8.210s 1662.742us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
otp_ctrl_macro_errs 2.580s 760.149us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
otp_ctrl_macro_errs 2.580s 760.149us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 15.510s 3524.306us 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.880s 419.117us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 13.460s 1810.055us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 7.820s 606.783us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 7.820s 606.783us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 7.820s 606.783us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 7.820s 606.783us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 7.820s 606.783us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 8.210s 1662.742us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 7.820s 606.783us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 8.210s 1662.742us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 115.160s 43667.621us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.580s 536.688us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 8.210s 1662.742us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 8.210s 1662.742us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.580s 760.149us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 15.660s 7930.012us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.110s 31.065us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 17851170490820103566148152678046781417023990785658899069711312256909073384604 1975
UVM_INFO @ 760149192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 39489256126164879709789655004677252701118163888418006153615861866481777349869 92
UVM_INFO @ 31065192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---