Simulation Results: pattgen

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.49 %
  • code
  • 98.87 %
  • assert
  • 98.17 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 35.787us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 21.325us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 2.000s 76.494us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 147.037us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 22.581us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 36.900us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 2.000s 76.494us 1 1 100.00
pattgen_csr_aliasing 1.000s 22.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 2.000s 626.957us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 8.000s 1132.350us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 96.589us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 143.000s 46632.630us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 24.639us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 2.000s 47.387us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 1.000s 125.598us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 1.000s 125.598us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 21.325us 1 1 100.00
pattgen_csr_rw 2.000s 76.494us 1 1 100.00
pattgen_csr_aliasing 1.000s 22.581us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 116.826us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 21.325us 1 1 100.00
pattgen_csr_rw 2.000s 76.494us 1 1 100.00
pattgen_csr_aliasing 1.000s 22.581us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 116.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 324.438us 1 1 100.00
pattgen_sec_cm 1.000s 39.688us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 324.438us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 20.000s 9786.480us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 37.730us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
pattgen_stress_all_with_rand_reset 73231507675488849832484707304191244273926813318844098321412314459022780020579 166
UVM_ERROR @ 4569804426 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4569804426 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 4570179429 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]