Simulation Results: pwrmgr

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.18 %
  • code
  • 97.39 %
  • assert
  • 98.96 %
  • func
  • 98.19 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.04 %
  • toggle
  • 99.44 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.730s 27.119us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.730s 33.192us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.610s 29.577us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.730s 187.660us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.900s 236.402us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.010s 74.281us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.610s 29.577us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 236.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.890s 524.116us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.890s 524.116us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.780s 34.686us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 53.119us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 2.700s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 1.020s 125.438us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 2.700s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.980s 517.497us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.860s 298.179us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.680s 87.595us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 4.390s 1282.061us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.660s 111.499us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.090s 30.642us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.090s 30.642us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.730s 33.192us 1 1 100.00
pwrmgr_csr_rw 0.610s 29.577us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 236.402us 1 1 100.00
pwrmgr_same_csr_outstanding 0.730s 32.609us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.730s 33.192us 1 1 100.00
pwrmgr_csr_rw 0.610s 29.577us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 236.402us 1 1 100.00
pwrmgr_same_csr_outstanding 0.730s 32.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.990s 117.265us 1 1 100.00
pwrmgr_sec_cm 1.330s 470.160us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.330s 470.160us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.330s 470.160us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.990s 117.265us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.000s 939.792us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.980s 517.497us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.670s 790.863us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.030s 102.112us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.640s 38.189us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.330s 470.160us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.330s 470.160us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.330s 470.160us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.570s 29.789us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.670s 53.970us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.830s 699.702us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.610s 29.577us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.610s 29.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.760s 104.566us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 6.160s 2357.694us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 110033175088149775499149822684491989318348971084074014820510381399153403545471 164
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 30937630235270239872207822508199238847861790128137230925965604499931034954922 79
UVM_ERROR @ 104566112 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 104566112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---