Simulation Results: rom_ctrl/32kb

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.97 %
  • code
  • 99.39 %
  • assert
  • 96.66 %
  • func
  • 97.85 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 97.92 %
  • toggle
  • 99.80 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.690s 314.065us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.590s 128.680us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.840s 1009.835us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.940s 210.210us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.960s 299.521us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.250s 598.933us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.840s 1009.835us 1 1 100.00
rom_ctrl_csr_aliasing 3.960s 299.521us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.260s 124.748us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.110s 294.208us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.350s 179.293us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 9.270s 1891.202us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 9.540s 3994.361us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.810s 356.872us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.480s 166.999us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.480s 166.999us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.590s 128.680us 1 1 100.00
rom_ctrl_csr_rw 4.840s 1009.835us 1 1 100.00
rom_ctrl_csr_aliasing 3.960s 299.521us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.720s 1050.624us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.590s 128.680us 1 1 100.00
rom_ctrl_csr_rw 4.840s 1009.835us 1 1 100.00
rom_ctrl_csr_aliasing 3.960s 299.521us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.720s 1050.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 58.730s 1797.000us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.870s 2204.355us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 201.020s 1712.094us 1 1 100.00
rom_ctrl_tl_intg_err 43.850s 714.025us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 201.020s 1712.094us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 201.020s 1712.094us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 58.730s 1797.000us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 58.730s 1797.000us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 58.730s 1797.000us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 58.730s 1797.000us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 58.730s 1797.000us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 201.020s 1712.094us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 201.020s 1712.094us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.690s 314.065us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.690s 314.065us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.690s 314.065us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 43.850s 714.025us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 58.730s 1797.000us 1 1 100.00
rom_ctrl_kmac_err_chk 9.540s 3994.361us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 58.730s 1797.000us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 58.730s 1797.000us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 58.730s 1797.000us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.870s 2204.355us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 201.020s 1712.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 341.350s 8815.042us 1 1 100.00