Simulation Results: rom_ctrl/64kb

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.10 %
  • code
  • 99.45 %
  • assert
  • 97.24 %
  • func
  • 97.61 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.51 %
  • toggle
  • 99.52 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.520s 1897.063us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 11.150s 1224.111us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.150s 214.209us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.790s 698.641us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.320s 209.156us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.420s 216.140us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.150s 214.209us 1 1 100.00
rom_ctrl_csr_aliasing 6.320s 209.156us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.730s 699.992us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.640s 3116.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 10.220s 2784.780us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 17.810s 2532.881us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.590s 380.507us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 8.190s 361.372us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.560s 1537.874us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.560s 1537.874us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.150s 1224.111us 1 1 100.00
rom_ctrl_csr_rw 6.150s 214.209us 1 1 100.00
rom_ctrl_csr_aliasing 6.320s 209.156us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.570s 292.778us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.150s 1224.111us 1 1 100.00
rom_ctrl_csr_rw 6.150s 214.209us 1 1 100.00
rom_ctrl_csr_aliasing 6.320s 209.156us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.570s 292.778us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.020s 8891.001us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 41.070s 6379.997us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 463.420s 1314.908us 1 1 100.00
rom_ctrl_tl_intg_err 52.860s 363.755us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 463.420s 1314.908us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 463.420s 1314.908us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.020s 8891.001us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.020s 8891.001us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.020s 8891.001us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.020s 8891.001us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.020s 8891.001us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 463.420s 1314.908us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 463.420s 1314.908us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.520s 1897.063us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.520s 1897.063us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.520s 1897.063us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 52.860s 363.755us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.020s 8891.001us 1 1 100.00
rom_ctrl_kmac_err_chk 13.590s 380.507us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.020s 8891.001us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.020s 8891.001us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 151.020s 8891.001us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 41.070s 6379.997us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 463.420s 1314.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 108.840s 8288.684us 1 1 100.00