Simulation Results: rstmgr

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.13 %
  • code
  • 99.33 %
  • assert
  • 98.53 %
  • func
  • 96.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.89 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.330s 248.067us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.110s 144.113us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.760s 85.361us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.500s 275.815us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.380s 387.541us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.140s 170.826us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.760s 85.361us 1 1 100.00
rstmgr_csr_aliasing 2.380s 387.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.700s 124.237us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.060s 118.820us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.870s 108.527us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.410s 1028.368us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.410s 1028.368us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.410s 1028.368us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.410s 1028.368us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 13.920s 5773.961us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.820s 73.649us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.940s 172.565us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.940s 172.565us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.110s 144.113us 1 1 100.00
rstmgr_csr_rw 0.760s 85.361us 1 1 100.00
rstmgr_csr_aliasing 2.380s 387.541us 1 1 100.00
rstmgr_same_csr_outstanding 1.220s 244.867us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.110s 144.113us 1 1 100.00
rstmgr_csr_rw 0.760s 85.361us 1 1 100.00
rstmgr_csr_aliasing 2.380s 387.541us 1 1 100.00
rstmgr_same_csr_outstanding 1.220s 244.867us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 18.990s 17208.624us 1 1 100.00
rstmgr_tl_intg_err 2.320s 826.787us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 18.990s 17208.624us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 18.990s 17208.624us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.320s 826.787us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.950s 187.774us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.380s 2687.765us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.410s 302.996us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 18.990s 17208.624us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 85.361us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 85.361us 1 1 100.00