Simulation Results: rv_timer

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.00 %
  • code
  • 100.00 %
  • assert
  • 98.41 %
  • func
  • 95.59 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.820s 238.319us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.530s 12.663us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.570s 40.108us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.260s 91.106us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.660s 40.702us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.870s 425.254us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.570s 40.108us 1 1 100.00
rv_timer_csr_aliasing 0.660s 40.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.660s 2261.031us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.400s 1236.441us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.590s 1029.038us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.590s 1029.038us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.660s 6994.176us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.530s 14.101us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.620s 32.099us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.840s 186.015us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.840s 186.015us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.530s 12.663us 1 1 100.00
rv_timer_csr_rw 0.570s 40.108us 1 1 100.00
rv_timer_csr_aliasing 0.660s 40.702us 1 1 100.00
rv_timer_same_csr_outstanding 0.600s 60.971us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.530s 12.663us 1 1 100.00
rv_timer_csr_rw 0.570s 40.108us 1 1 100.00
rv_timer_csr_aliasing 0.660s 40.702us 1 1 100.00
rv_timer_same_csr_outstanding 0.600s 60.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.770s 92.609us 1 1 100.00
rv_timer_tl_intg_err 0.930s 326.566us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.930s 326.566us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.620s 71.159us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.570s 364.422us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 8.230s 5772.716us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 92456974398951820932563667509467151170121041146362072540928854928367530681784 75
UVM_INFO @ 71158669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 57349230207114171561325931087918656987722607117268025615932070553639129922967 75
UVM_INFO @ 2261030663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 28931762112962967196773443934061673786756542413583318034353589244492199590055 75
UVM_INFO @ 364421545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---