Simulation Results: spi_host

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.03 %
  • code
  • 95.03 %
  • assert
  • 94.13 %
  • func
  • 89.92 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 6.000s 239.491us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 44.386us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 17.659us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 118.296us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 32.023us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 89.332us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 17.659us 1 1 100.00
spi_host_csr_aliasing 2.000s 32.023us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 16.304us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 119.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 28.423us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 231.411us 1 1 100.00
spi_host_error_cmd 2.000s 62.933us 1 1 100.00
spi_host_event 10.000s 2766.431us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 81.743us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 81.743us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 81.743us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 8.000s 965.353us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 6.000s 277.531us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 25.768us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 81.743us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 81.743us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 6.000s 239.491us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 6.000s 239.491us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 23.000s 7114.438us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 744.869us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 30.000s 1913.021us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 125.618us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 231.411us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 16.024us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 23.053us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 455.156us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 455.156us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 44.386us 1 1 100.00
spi_host_csr_rw 2.000s 17.659us 1 1 100.00
spi_host_csr_aliasing 2.000s 32.023us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 72.011us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 44.386us 1 1 100.00
spi_host_csr_rw 2.000s 17.659us 1 1 100.00
spi_host_csr_aliasing 2.000s 32.023us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 72.011us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 289.503us 1 1 100.00
spi_host_sec_cm 2.000s 65.740us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 289.503us 1 1 100.00