Simulation Results: sram_ctrl/main

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.90 %
  • code
  • 96.81 %
  • assert
  • 97.28 %
  • func
  • 93.60 %
  • block
  • 96.08 %
  • line
  • 96.81 %
  • branch
  • 94.33 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 798.990us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 15.377us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.492us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 397.698us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 35.095us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 552.294us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 13.492us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 35.095us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 227.000s 94391.828us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 55.000s 11428.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 18.000s 14828.986us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 103.000s 6528.438us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 151.000s 63025.772us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 38.000s 27835.282us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 54.000s 58349.364us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 30.000s 13418.644us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 392.859us 1 1 100.00
sram_ctrl_partial_access_b2b 232.000s 18925.288us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 2565.000us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 2783.284us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 2799.140us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 13.000s 1912.191us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 357.042us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 212.000s 167554.972us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 18.214us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 299.531us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 299.531us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 15.377us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.492us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 35.095us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 54.464us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 15.377us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.492us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 35.095us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 54.464us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 7280.293us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1443.714us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 795.900us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1443.714us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 795.900us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 1912.191us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 1912.191us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.492us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 30.000s 13418.644us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.000s 13418.644us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.000s 13418.644us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 54.000s 58349.364us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 4444.865us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 7280.293us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 704.972us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 798.990us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 798.990us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 30.000s 13418.644us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1443.714us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 54.000s 58349.364us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1443.714us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1443.714us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 798.990us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1443.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 8.000s 612.951us 1 1 100.00