Simulation Results: sysrst_ctrl

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.12 %
  • code
  • 92.42 %
  • assert
  • 94.25 %
  • func
  • 65.69 %
  • line
  • 97.08 %
  • branch
  • 97.33 %
  • cond
  • 94.85 %
  • toggle
  • 99.77 %
  • FSM
  • 73.08 %
Validation stages
V1
88.89%
V2
94.44%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.060s 2136.485us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.140s 2490.330us 1 1 100.00
combo_detect_ec_rst 0 1 0.00
sysrst_ctrl_combo_detect_ec_rst 4.750s 2391.323us 0 1 0.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.390s 2531.510us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.470s 6188.837us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.660s 2120.871us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 68.170s 38971.391us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 7.570s 2812.914us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 5.220s 2080.680us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.660s 2120.871us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.570s 2812.914us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 16.110s 31053.310us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 27.680s 131628.855us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.330s 3466.855us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.490s 3387.124us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.070s 2516.775us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.290s 2131.718us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 7.210s 3278.959us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.510s 2618.135us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 3.110s 4272.803us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 74.480s 40643.130us 1 1 100.00
stress_all 0 1 0.00
sysrst_ctrl_stress_all 4.630s 17566.243us 0 1 0.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.320s 2019.049us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.580s 2028.075us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.110s 2048.685us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.110s 2048.685us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.470s 6188.837us 1 1 100.00
sysrst_ctrl_csr_rw 1.660s 2120.871us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.570s 2812.914us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 19.310s 7748.524us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.470s 6188.837us 1 1 100.00
sysrst_ctrl_csr_rw 1.660s 2120.871us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.570s 2812.914us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 19.310s 7748.524us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 74.920s 42010.506us 1 1 100.00
sysrst_ctrl_tl_intg_err 41.070s 22250.791us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 41.070s 22250.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 11.340s 22337.315us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * 1 test run
sysrst_ctrl_combo_detect_ec_rst 50998959343570289719404163961969285502024915373020311430591947761336333426754 658
UVM_INFO @ 2391322707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  1 test run
sysrst_ctrl_stress_all 83343052263663115434118119307650464334901874555947530175692922261498239640490 668
UVM_INFO @ 11085720388 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 11720720388 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 11761680843 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_ultra_low_pwr_vseq
UVM_INFO @ 13761024173 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:106) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Starting the body from ultra_low_pwr_vseq