Simulation Results: uart

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.24 %
  • code
  • 95.90 %
  • assert
  • 97.12 %
  • func
  • 56.70 %
  • line
  • 99.17 %
  • branch
  • 96.97 %
  • cond
  • 95.92 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.550s 965.465us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.760s 27.114us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.620s 16.076us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.750s 220.231us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.860s 48.698us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.850s 80.864us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.620s 16.076us 1 1 100.00
uart_csr_aliasing 0.860s 48.698us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 31.290s 43586.654us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.550s 965.465us 1 1 100.00
uart_tx_rx 31.290s 43586.654us 1 1 100.00
parity_error 2 2 100.00
uart_intr 11.050s 20519.144us 1 1 100.00
uart_rx_parity_err 70.740s 125403.219us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 31.290s 43586.654us 1 1 100.00
uart_intr 11.050s 20519.144us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 156.100s 309112.723us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 25.840s 40525.410us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 30.310s 24061.820us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 11.050s 20519.144us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 11.050s 20519.144us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 11.050s 20519.144us 1 1 100.00
perf 1 1 100.00
uart_perf 821.970s 21840.000us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.990s 1982.626us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.990s 1982.626us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 25.810s 25002.613us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.110s 4185.740us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.330s 822.946us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 24.790s 3813.019us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 554.020s 150659.650us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 347.510s 597868.410us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.630s 15.099us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.680s 15.341us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.640s 108.674us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.640s 108.674us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.760s 27.114us 1 1 100.00
uart_csr_rw 0.620s 16.076us 1 1 100.00
uart_csr_aliasing 0.860s 48.698us 1 1 100.00
uart_same_csr_outstanding 0.680s 41.142us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.760s 27.114us 1 1 100.00
uart_csr_rw 0.620s 16.076us 1 1 100.00
uart_csr_aliasing 0.860s 48.698us 1 1 100.00
uart_same_csr_outstanding 0.680s 41.142us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.760s 44.570us 1 1 100.00
uart_tl_intg_err 1.070s 95.092us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.070s 95.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 20.070s 6691.974us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 4970132241465173726633954720180596202888153417544896447954853661331711393989 81
UVM_ERROR @ 23268043949 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 23268054475 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 23268065001 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (189 [0xbd] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 23321000255 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0