Simulation Results: adc_ctrl

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.82 %
  • code
  • 92.74 %
  • assert
  • 91.73 %
  • func
  • 12.99 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 86.06 %
  • toggle
  • 99.53 %
  • FSM
  • 83.78 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 3.080s 5894.825us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.520s 672.040us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.500s 511.365us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 2.200s 2404.491us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.120s 952.200us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.250s 327.033us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.500s 511.365us 1 1 100.00
adc_ctrl_csr_aliasing 3.120s 952.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.200s 467.661us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.050s 383.524us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.660s 287.062us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.640s 351.466us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.740s 282.750us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.730s 421.526us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.880s 526.117us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.240s 398.840us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 4.930s 3041.622us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 34.880s 42436.805us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 37.030s 82272.670us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.230s 1045.425us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.120s 325.833us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.780s 552.852us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.270s 982.654us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.270s 982.654us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.520s 672.040us 1 1 100.00
adc_ctrl_csr_rw 1.500s 511.365us 1 1 100.00
adc_ctrl_csr_aliasing 3.120s 952.200us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.630s 4545.151us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.520s 672.040us 1 1 100.00
adc_ctrl_csr_rw 1.500s 511.365us 1 1 100.00
adc_ctrl_csr_aliasing 3.120s 952.200us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.630s 4545.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 6.610s 4001.919us 1 1 100.00
adc_ctrl_tl_intg_err 8.600s 8001.110us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 8.600s 8001.110us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.720s 672.650us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 19992715569074840362560244941587256039246854117052911749733938727370574194981 386
UVM_INFO @ 467661072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 102704887653916371903651635156360203911489574025765174340147753719373653207833 386
UVM_INFO @ 383524207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 38556241043731897129930437694652607500694360440030101191964811959948342161662 386
UVM_INFO @ 287061540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 16338730795221565459156819859447477652227543532796328155362735784096926431372 386
UVM_INFO @ 351465927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 72776841006102559306075232199672618831885935073852227009299464018836721285416 386
UVM_INFO @ 282750027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 45162145740406842047218920725068946444023392848130337345638407091058634708063 386
UVM_INFO @ 421526006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 106840260355762677822392981926570099152759659301468333980279468977583766592522 386
UVM_INFO @ 398840363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 48268467177303938072625928350740492123939006071246150956099962276934644335820 386
UVM_INFO @ 526117176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 20440328580698539639448729477159405072556874720054602594157334891734688092556 399
UVM_INFO @ 672649733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 38417332420043807533644083130734548548673836808354461141798693660261114809451 397
UVM_INFO @ 1045424943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---