Simulation Results: aes/masked

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.48 %
  • code
  • 93.62 %
  • assert
  • 98.23 %
  • func
  • 76.60 %
  • block
  • 94.30 %
  • line
  • 95.99 %
  • branch
  • 87.18 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 59.021us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 111.779us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 78.278us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 64.659us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 801.683us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 186.581us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 158.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 64.659us 1 1 100.00
aes_csr_aliasing 3.000s 186.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 111.779us 1 1 100.00
aes_config_error 2.000s 184.680us 1 1 100.00
aes_stress 4.000s 126.601us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 111.779us 1 1 100.00
aes_config_error 2.000s 184.680us 1 1 100.00
aes_stress 4.000s 126.601us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 126.601us 1 1 100.00
aes_b2b 5.000s 115.884us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 126.601us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 111.779us 1 1 100.00
aes_config_error 2.000s 184.680us 1 1 100.00
aes_stress 4.000s 126.601us 1 1 100.00
aes_alert_reset 4.000s 337.830us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 73.547us 1 1 100.00
aes_config_error 2.000s 184.680us 1 1 100.00
aes_alert_reset 4.000s 337.830us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 98.102us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 404.102us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 337.830us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 126.601us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 126.601us 1 1 100.00
aes_sideload 3.000s 103.565us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 230.653us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 22.000s 3531.494us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 54.045us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 101.505us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 101.505us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 78.278us 1 1 100.00
aes_csr_rw 2.000s 64.659us 1 1 100.00
aes_csr_aliasing 3.000s 186.581us 1 1 100.00
aes_same_csr_outstanding 2.000s 121.788us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 78.278us 1 1 100.00
aes_csr_rw 2.000s 64.659us 1 1 100.00
aes_csr_aliasing 3.000s 186.581us 1 1 100.00
aes_same_csr_outstanding 2.000s 121.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 7.000s 411.613us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 321.167us 1 1 100.00
aes_control_fi 2.000s 47.663us 1 1 100.00
aes_cipher_fi 3.000s 64.927us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 102.770us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 102.770us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 102.770us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 102.770us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 298.972us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 545.660us 1 1 100.00
aes_tl_intg_err 2.000s 321.923us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 321.923us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 337.830us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 102.770us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 102.770us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 111.779us 1 1 100.00
aes_stress 4.000s 126.601us 1 1 100.00
aes_alert_reset 4.000s 337.830us 1 1 100.00
aes_core_fi 3.000s 221.114us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 184.680us 1 1 100.00
aes_stress 4.000s 126.601us 1 1 100.00
aes_core_fi 3.000s 221.114us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 102.770us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 59.194us 1 1 100.00
aes_stress 4.000s 126.601us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 126.601us 1 1 100.00
aes_sideload 3.000s 103.565us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 59.194us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 59.194us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 59.194us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 59.194us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 59.194us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 126.601us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 126.601us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 321.167us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 321.167us 1 1 100.00
aes_control_fi 2.000s 47.663us 1 1 100.00
aes_cipher_fi 3.000s 64.927us 1 1 100.00
aes_ctr_fi 2.000s 64.076us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 321.167us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 321.167us 1 1 100.00
aes_control_fi 2.000s 47.663us 1 1 100.00
aes_cipher_fi 3.000s 64.927us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 64.927us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 321.167us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 321.167us 1 1 100.00
aes_control_fi 2.000s 47.663us 1 1 100.00
aes_ctr_fi 2.000s 64.076us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 321.167us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 321.167us 1 1 100.00
aes_control_fi 2.000s 47.663us 1 1 100.00
aes_cipher_fi 3.000s 64.927us 1 1 100.00
aes_ctr_fi 2.000s 64.076us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 337.830us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 321.167us 1 1 100.00
aes_control_fi 2.000s 47.663us 1 1 100.00
aes_cipher_fi 3.000s 64.927us 1 1 100.00
aes_ctr_fi 2.000s 64.076us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 321.167us 1 1 100.00
aes_control_fi 2.000s 47.663us 1 1 100.00
aes_cipher_fi 3.000s 64.927us 1 1 100.00
aes_ctr_fi 2.000s 64.076us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 321.167us 1 1 100.00
aes_control_fi 2.000s 47.663us 1 1 100.00
aes_ctr_fi 2.000s 64.076us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 1 100.00
aes_fi 3.000s 321.167us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 321.167us 1 1 100.00
aes_control_fi 2.000s 47.663us 1 1 100.00
aes_cipher_fi 3.000s 64.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 5.000s 393.865us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 4916512180360201012017164412575849936644177506406149738142180645746666338668 234
UVM_INFO @ 393865408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---