Simulation Results

Simulation Results: chip

08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
77.12 %

code
85.41 %

assert
97.50 %

func
48.44 %

line
94.39 %

branch
93.74 %

cond
90.49 %

toggle
91.30 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		77.34%
V2S		50.00%
V3		69.23%
unmapped		63.64%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	165.030s	2821.320us	1	1	100.00
	chip_sw_example_rom	89.410s	2590.991us	1	1	100.00
	chip_sw_example_manufacturer	186.320s	2877.850us	1	1	100.00
	chip_sw_example_concurrency	188.560s	3370.976us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	152.440s	5182.938us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	238.610s	5042.595us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	231.800s	3636.988us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4168.620s	29611.750us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	719.370s	10888.657us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4168.620s	29611.750us	1	1	100.00
	chip_csr_rw	238.610s	5042.595us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	7.420s	55.880us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	299.850s	4396.418us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	299.850s	4396.418us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	299.850s	4396.418us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	409.540s	4475.035us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	409.540s	4475.035us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	366.630s	4316.297us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	359.040s	4238.401us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	410.130s	4713.042us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1097.600s	8165.762us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	378.510s	4407.619us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	711.390s	8650.343us	1	1	100.00

215/278 passed

77.34 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	241.620s	5287.658us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	241.620s	5287.658us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	219.400s	3075.226us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	168.660s	2782.125us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	200.810s	3706.093us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	348.050s	6419.699us	1	1	100.00
	chip_tap_straps_testunlock0	201.790s	4620.810us	1	1	100.00
	chip_tap_straps_rma	462.810s	7517.358us	1	1	100.00
	chip_tap_straps_prod	90.180s	2804.543us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	163.150s	3302.263us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	866.780s	10063.682us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	420.020s	6264.016us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	420.020s	6264.016us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	621.250s	7582.081us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	683.300s	9788.907us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	324.070s	3425.375us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	546.750s	5963.949us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3749.500s	19403.597us	1	1	100.00
	chip_sw_aes_enc_jitter_en	180.930s	3356.062us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	728.350s	6339.293us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	181.310s	3185.619us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	967.180s	8821.107us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	181.720s	2663.991us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	312.480s	4247.513us	1	1	100.00
	chip_sw_clkmgr_jitter	151.560s	2856.829us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	218.760s	3163.405us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	266.060s	4549.373us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	213.920s	5291.236us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	199.590s	3267.781us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	213.920s	5291.236us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	177.550s	3113.637us	1	1	100.00
	chip_sw_aes_smoketest	160.520s	3259.868us	1	1	100.00
	chip_sw_aon_timer_smoketest	174.930s	3806.307us	1	1	100.00
	chip_sw_clkmgr_smoketest	156.200s	2507.109us	1	1	100.00
	chip_sw_csrng_smoketest	114.240s	2851.715us	1	1	100.00
	chip_sw_entropy_src_smoketest	691.100s	5442.313us	1	1	100.00
	chip_sw_gpio_smoketest	188.690s	3015.953us	1	1	100.00
	chip_sw_hmac_smoketest	195.580s	3693.562us	1	1	100.00
	chip_sw_kmac_smoketest	201.200s	3584.550us	1	1	100.00
	chip_sw_otbn_smoketest	1097.360s	8451.114us	1	1	100.00
	chip_sw_pwrmgr_smoketest	318.510s	7102.027us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	241.900s	5667.133us	1	1	100.00
	chip_sw_rv_plic_smoketest	218.560s	3779.677us	1	1	100.00
	chip_sw_rv_timer_smoketest	189.620s	3166.231us	1	1	100.00
	chip_sw_rstmgr_smoketest	135.500s	2673.353us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	135.110s	2401.284us	1	1	100.00
	chip_sw_uart_smoketest	157.170s	3517.747us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	154.040s	3311.055us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	283.470s	4643.456us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	8080.700s	63370.075us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3117.550s	15883.822us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	116.952s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	185.460s	3114.283us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	237.980s	3458.269us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7377.640s	55049.777us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7376.250s	57318.712us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	152.160s	2989.716us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	152.160s	2989.716us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	4168.620s	29611.750us	1	1	100.00
	chip_same_csr_outstanding	3162.350s	31183.289us	1	1	100.00
	chip_csr_hw_reset	152.440s	5182.938us	1	1	100.00
	chip_csr_rw	238.610s	5042.595us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	4168.620s	29611.750us	1	1	100.00
	chip_same_csr_outstanding	3162.350s	31183.289us	1	1	100.00
	chip_csr_hw_reset	152.440s	5182.938us	1	1	100.00
	chip_csr_rw	238.610s	5042.595us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	19.810s	381.519us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.900s	44.522us	1	1	100.00
	xbar_smoke_large_delays	65.610s	9452.867us	1	1	100.00
	xbar_smoke_slow_rsp	58.970s	5568.992us	1	1	100.00
	xbar_random_zero_delays	29.930s	465.469us	1	1	100.00
	xbar_random_large_delays	141.770s	23537.235us	1	1	100.00
	xbar_random_slow_rsp	57.640s	6098.921us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	12.070s	149.056us	1	1	100.00
	xbar_error_and_unmapped_addr	30.230s	1137.192us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	54.330s	2563.305us	1	1	100.00
	xbar_error_and_unmapped_addr	30.230s	1137.192us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	66.370s	2982.099us	1	1	100.00
	xbar_access_same_device_slow_rsp	271.930s	30979.980us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	22.500s	317.939us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	147.060s	5001.816us	1	1	100.00
	xbar_stress_all_with_error	258.080s	9099.156us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	192.800s	1644.256us	1	1	100.00
	xbar_stress_all_with_reset_error	219.290s	827.439us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3117.550s	15883.822us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2636.150s	26306.936us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3026.720s	15709.304us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	156.258s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	21.623s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	22.436s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.339s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	7.463s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	150.859s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	33.149s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	31.521s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.542s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.233s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	176.345s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	48.998s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	22.263s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	57.149s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	22.386s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18.310s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	20.710s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	24.780s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20.600s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	19.160s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.660s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	31.740s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	22.120s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	20.330s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	19.960s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	21.500s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	19.510s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.770s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	20.510s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	20.180s	10.340us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	59.814s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	64.707s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	61.236s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	51.875s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	54.350s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	5953.550s	29906.084us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	3135.470s	18473.910us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	5909.710s	29285.579us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3299.440s	17954.195us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2982.060s	34923.974us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2982.060s	34923.974us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	207.880s	3586.292us	1	1	100.00
	chip_sw_aes_enc_jitter_en	180.930s	3356.062us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	172.910s	3242.638us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	203.160s	3896.117us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1358.170s	10993.314us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	184.160s	3164.947us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	351.570s	5874.022us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	420.170s	6056.381us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	498.900s	5269.383us	1	1	100.00
	chip_plic_all_irqs_10	274.800s	4251.762us	1	1	100.00
	chip_plic_all_irqs_20	339.550s	4666.044us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	182.170s	3366.582us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1164.090s	14992.662us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	242.830s	4276.519us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	157.810s	2960.941us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.160s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	981.030s	7149.354us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	808.060s	7465.796us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	803.400s	8017.096us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9344.720s	255002.573us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	223.660s	3729.160us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	318.510s	7102.027us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	223.660s	3729.160us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	484.640s	7992.907us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	484.640s	7992.907us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	310.230s	7665.191us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	386.200s	5491.448us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	647.850s	6356.954us	1	1	100.00
	chip_sw_aes_idle	203.160s	3896.117us	1	1	100.00
	chip_sw_hmac_enc_idle	159.580s	2748.955us	1	1	100.00
	chip_sw_kmac_idle	184.970s	3569.909us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	305.080s	5038.711us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	266.440s	4585.840us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	376.480s	5314.569us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	258.740s	4250.448us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	1139.260s	13574.702us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	365.200s	4101.929us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	409.680s	4507.268us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	401.550s	4039.326us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	406.690s	5062.907us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	451.610s	4575.539us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	381.600s	5319.368us	1	1	100.00
	chip_sw_ast_clk_outputs	621.250s	7582.081us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	314.600s	5932.519us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	401.550s	4039.326us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	406.690s	5062.907us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	324.070s	3425.375us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	546.750s	5963.949us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3749.500s	19403.597us	1	1	100.00
	chip_sw_aes_enc_jitter_en	180.930s	3356.062us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	728.350s	6339.293us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	181.310s	3185.619us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	967.180s	8821.107us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	181.720s	2663.991us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	312.480s	4247.513us	1	1	100.00
	chip_sw_clkmgr_jitter	151.560s	2856.829us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	142.190s	3419.748us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	384.320s	5353.440us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	611.110s	7013.860us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4048.160s	25240.490us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	173.790s	2919.466us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	185.030s	3756.408us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	692.530s	8563.351us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	222.530s	3513.850us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	409.200s	5476.327us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1470.130s	25011.140us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	2843.720s	21574.096us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	621.250s	7582.081us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	371.960s	4663.081us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	244.890s	3942.892us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	420.170s	6056.381us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	981.030s	7149.354us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2185.640s	24962.367us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	161.370s	2901.354us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	531.860s	8296.823us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	214.710s	2984.164us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	3116.590s	18943.619us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	187.150s	3038.597us	1	1	100.00
	chip_sw_edn_entropy_reqs	926.550s	8082.659us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	187.150s	3038.597us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2185.640s	24962.367us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	114.690s	2238.418us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1228.410s	17992.021us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	650.260s	6294.525us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	546.750s	5963.949us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	370.950s	4016.542us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	324.070s	3425.375us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3858.030s	43124.204us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1228.410s	17992.021us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	197.080s	4038.057us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1164.080s	9189.087us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	161.210s	2536.783us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3858.030s	43124.204us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	161.210s	2536.783us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	161.210s	2536.783us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	161.210s	2536.783us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	161.210s	2536.783us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	420.170s	6056.381us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	241.370s	9649.344us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	539.730s	5498.333us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	408.260s	5183.181us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	408.260s	5183.181us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	184.410s	3490.331us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	181.310s	3185.619us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	159.580s	2748.955us	1	1	100.00
chip_sw_hmac_all_configurations				0	1	0.00
	chip_sw_hmac_oneshot	1662.270s	12026.881us	0	1	0.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1647.690s	12018.539us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	468.960s	5171.351us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	442.880s	4685.961us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	519.970s	5509.755us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	352.650s	4429.403us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1164.080s	9189.087us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	967.180s	8821.107us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1676.260s	12115.813us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1358.170s	10993.314us	1	1	100.00
chip_sw_keymgr_sideload_otbn				1	1	100.00
	chip_sw_keymgr_sideload_otbn	3745.220s	16072.565us	1	1	100.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	158.790s	3114.068us	1	1	100.00
	chip_sw_kmac_mode_kmac	229.070s	3758.635us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	181.720s	2663.991us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1164.080s	9189.087us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	411.290s	6800.267us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	149.480s	2929.204us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1173.560s	8949.632us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	184.970s	3569.909us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	351.570s	5874.022us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	348.050s	6419.699us	1	1	100.00
	chip_tap_straps_rma	462.810s	7517.358us	1	1	100.00
	chip_tap_straps_prod	90.180s	2804.543us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	142.600s	3359.081us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	411.290s	6800.267us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	411.290s	6800.267us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	411.290s	6800.267us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1586.520s	12333.723us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	161.210s	2536.783us	0	1	0.00
	chip_sw_flash_rma_unlocked	3858.030s	43124.204us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	225.680s	3312.233us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	549.800s	5968.346us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	416.850s	6007.096us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	457.000s	7124.714us	0	1	0.00
	chip_sw_lc_ctrl_transition	411.290s	6800.267us	1	1	100.00
	chip_sw_keymgr_key_derivation	1164.080s	9189.087us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	383.830s	10107.987us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	428.770s	9334.235us	1	1	100.00
	chip_prim_tl_access	241.370s	9649.344us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	314.600s	5932.519us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	365.200s	4101.929us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	409.680s	4507.268us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	401.550s	4039.326us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	406.690s	5062.907us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	451.610s	4575.539us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	381.600s	5319.368us	1	1	100.00
	chip_tap_straps_dev	348.050s	6419.699us	1	1	100.00
	chip_tap_straps_rma	462.810s	7517.358us	1	1	100.00
	chip_tap_straps_prod	90.180s	2804.543us	1	1	100.00
	chip_rv_dm_lc_disabled	202.900s	7443.117us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	155.490s	3572.550us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	83.420s	3427.464us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	86.640s	2774.517us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	79.190s	3293.043us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1333.530s	26994.359us	1	1	100.00
	chip_rv_dm_lc_disabled	202.900s	7443.117us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	743.250s	10294.451us	0	1	0.00
	chip_sw_lc_walkthrough_prod	629.910s	10326.611us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	623.920s	8558.741us	1	1	100.00
	chip_sw_lc_walkthrough_rma	346.390s	6929.616us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1333.530s	26994.359us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	54.790s	2339.682us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	70.910s	2749.437us	1	1	100.00
	rom_volatile_raw_unlock	145.910s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3773.470s	16720.899us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3749.500s	19403.597us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	647.850s	6356.954us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	647.850s	6356.954us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	647.850s	6356.954us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	302.460s	3940.438us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	411.290s	6800.267us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1228.410s	17992.021us	1	1	100.00
	chip_sw_otbn_mem_scramble	302.460s	3940.438us	1	1	100.00
	chip_sw_keymgr_key_derivation	1164.080s	9189.087us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	400.610s	5228.545us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	175.770s	2713.106us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1228.410s	17992.021us	1	1	100.00
	chip_sw_otbn_mem_scramble	302.460s	3940.438us	1	1	100.00
	chip_sw_keymgr_key_derivation	1164.080s	9189.087us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	400.610s	5228.545us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	175.770s	2713.106us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	411.290s	6800.267us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	316.500s	5223.081us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	142.600s	3359.081us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	225.680s	3312.233us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	549.800s	5968.346us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	416.850s	6007.096us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	457.000s	7124.714us	0	1	0.00
	chip_sw_lc_ctrl_transition	411.290s	6800.267us	1	1	100.00
	chip_prim_tl_access	241.370s	9649.344us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	241.370s	9649.344us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	811.550s	7957.978us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	61.720s	2320.664us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	1188.320s	25937.825us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	200.940s	7527.755us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	259.470s	6840.747us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	432.620s	7884.171us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	673.250s	21591.406us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	499.540s	10290.068us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	484.640s	7992.907us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	458.860s	7303.153us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	435.110s	5130.874us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	61.720s	2320.664us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	205.460s	4336.287us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	242.280s	5142.100us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	351.850s	7650.665us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	165.230s	3090.595us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1321.280s	21146.322us	1	1	100.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	670.690s	7673.395us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1107.480s	12846.990us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1550.780s	26444.530us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	190.000s	3013.324us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	420.170s	6056.381us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	383.830s	10107.987us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	383.830s	10107.987us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				4	4	100.00
	chip_sw_pwrmgr_all_reset_reqs	1107.480s	12846.990us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1321.280s	21146.322us	1	1	100.00
	chip_sw_pwrmgr_wdog_reset	435.110s	5130.874us	1	1	100.00
	chip_sw_pwrmgr_smoketest	318.510s	7102.027us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	319.580s	5580.641us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	457.040s	5965.546us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	228.520s	4443.587us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1164.090s	14992.662us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	190.380s	3012.134us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	420.170s	6056.381us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	808.060s	7465.796us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	524.780s	4817.632us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	527.330s	4376.345us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	168.910s	3456.972us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	175.770s	2713.106us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	457.040s	5965.546us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	457.040s	5965.546us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	610.600s	10628.057us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	770.450s	13298.608us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	319.580s	5580.641us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	178.540s	2729.630us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	306.870s	5925.851us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	462.810s	7517.358us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	202.900s	7443.117us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	498.900s	5269.383us	1	1	100.00
	chip_plic_all_irqs_10	274.800s	4251.762us	1	1	100.00
	chip_plic_all_irqs_20	339.550s	4666.044us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	152.270s	2673.610us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	150.050s	3190.408us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3117.550s	15883.822us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	268.230s	3428.940us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	182.660s	2722.580us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	229.990s	3626.401us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	183.700s	2731.860us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	400.610s	5228.545us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	312.480s	4247.513us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	516.460s	8650.608us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	385.190s	7771.996us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	428.770s	9334.235us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	420.170s	6056.381us	1	1	100.00
	chip_sw_data_integrity_escalation	420.020s	6264.016us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	670.690s	7673.395us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1174.470s	25662.964us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	191.570s	3336.721us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	281.420s	3960.184us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	345.410s	4973.764us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1174.470s	25662.964us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1174.470s	25662.964us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2329.410s	20711.659us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2329.410s	20711.659us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	327.630s	6131.644us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2982.060s	34923.974us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	142.470s	2349.499us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	157.840s	2613.221us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	266.790s	3310.173us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	314.160s	3738.097us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	968.450s	7954.931us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5255.770s	31529.836us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1739.440s	11885.159us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	176.160s	2989.318us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	181.400s	2974.727us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				0	1	0.00
	chip_sw_rv_core_ibex_lockstep_glitch	80.230s	2786.269us	0	1	0.00

18/26 passed

69.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	10276.730s	70835.386us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1095.160s	6683.914us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	205.890s	4995.683us	0	1	0.00
	rom_e2e_jtag_debug_dev	226.910s	4251.559us	0	1	0.00
	rom_e2e_jtag_debug_rma	465.020s	7692.207us	0	1	0.00
rom_e2e_jtag_inject				1	3	33.33
	rom_e2e_jtag_inject_test_unlocked0	92.110s	2857.672us	0	1	0.00
	rom_e2e_jtag_inject_dev	67.430s	2469.385us	0	1	0.00
	rom_e2e_jtag_inject_rma	221.570s	5309.536us	1	1	100.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	48.953s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	313.650s	3783.966us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	337.750s	2952.430us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	928.070s	5831.607us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1188.220s	8793.196us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	239.410s	2571.429us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	603.690s	5815.406us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	147.870s	2408.206us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	184.570s	3380.523us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	322.600s	6677.917us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	252.860s	5062.958us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1107.480s	12846.990us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	205.890s	4995.683us	0	1	0.00
	rom_e2e_jtag_debug_dev	226.910s	4251.559us	0	1	0.00
	rom_e2e_jtag_debug_rma	465.020s	7692.207us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	368.610s	4786.719us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	420.170s	6056.381us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5473.300s	38901.455us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5473.300s	38901.455us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	146.600s	3118.730us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	409.540s	4475.035us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	2985.620s	19135.430us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	243.130s	3059.798us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	20.870s	10.300us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	5.190s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	149.300s	2755.504us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	217.330s	3010.450us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	273.750s	4018.079us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	9.146s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	165.860s	3415.371us	1	1	100.00
	ate_bootstrap_flash_erase	541.300s	10010.100us	0	1	0.00
	ate_bootstrap_one_frame	6531.650s	45726.651us	1	1	100.00
	ate_bootstrap_disjoint	10205.180s	85459.925us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	51956761522838646106649840933125365181755822252633137359852945441944328970731	None	---- STDERR ---- Another command (pid=2085511) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	4655398453130376707795877813476367865425727630245421344016895234128297571163	None	Another command (pid=555988) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=620529) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=566520) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	49272853802417696210472282020653754590696638948887610520357674631804501143271	None	Another command (pid=654366) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=605877) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=387509) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	39280966705383225981973288965778232211368020150946294509190368981004509932503	None	Another command (pid=671218) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=676393) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=677949) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	108398762706953411815723447733488664950561007634802980189337802055468090259993	None	Another command (pid=634916) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=598017) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=403154) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	75893581740213230605666940530939534704444707747793792336172194209967617934332	None	---- STDERR ---- Another command (pid=648966) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	87343769127664987073902281498183868069101942175254210569615328214477941503102	None	Another command (pid=593172) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=588017) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=584561) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	14535406737574194380655332095566830467972474240452941242658309888448009760459	None	Another command (pid=646900) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=583540) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=654366) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	71215061232568376253300445395634699596476530209484189699663339091045611226612	None	Another command (pid=657546) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=647653) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=648966) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	48073688683470492893044703699505613197439124645750481342663002774230722496960	None	Another command (pid=646900) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=583540) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=654366) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	87812403242034493888828824096509884198855177872087710572193117063129726118699	None	Another command (pid=600016) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=625286) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=633924) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	69565611063239193374147361567590070113511812075229587803961765049298190331620	None	Another command (pid=657546) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=647653) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=648966) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	44122079463993285392784470032564671133670849579883536566920744593019837765646	None	Another command (pid=598017) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=403154) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=646900) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	110050617470018734266492680844674549778858016187020005746445630540959202125363	None	Another command (pid=553720) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=586393) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=583136) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	55410851349434345402533600352897262615928042268010912033126510106635288467244	None	---- STDERR ---- Another command (pid=691521) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	115390576361460164358729728360176469316974068689619306472144571134008200092970	None	Another command (pid=588017) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=584561) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=389569) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	110683858191630001351069921438139998316262275132411885354034022565751578452120	None	Another command (pid=372646) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=437641) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=376639) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	54916369386335484648960059340486107604342170048268008019470840056934688408523	None	---- STDERR ---- Another command (pid=447353) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=459760) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	35946663292506178025420324331402097810139793664345501201785658767612897165777	None	Another command (pid=550069) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=554817) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=554239) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	40302843131412847411545619023256430456191613649364139910544373249383972845783	None	---- STDERR ---- Another command (pid=447353) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=459760) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	110477953291486965373237016633885316846277015296772890224768151815667422856309	None	Another command (pid=550069) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=554817) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=554239) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	25550982103547913089785605134630198033032879780047424668507695487389145754804	None	Another command (pid=598622) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=605877) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=387509) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	5535632636791574949375976308745654318122242765709049587283814531402039719909	None	Another command (pid=423948) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=565783) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=579181) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	13529402135956191740920024553660475149047896270637920244979848795057058664093	None	---- STDERR ---- Another command (pid=372646) is running. Waiting for it to complete on the server (server_pid=289941)... Another command (pid=437641) is running. Waiting for it to complete on the server (server_pid=289941)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				6 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	87765924083785568343788158497865073406306019846644062655805399354298593428861	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	31146650244746249603146183108064779227519182850161711212095305807033519541030	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	107528752980198051674026062029226360057018452298309325894912511452295283412633	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	56790682913503529605144981593003728394113276058029246365436125942590013222889	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	2181959210096876459928319477434070096194088488127236844116739887385551447405	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	30998070922219870856328755906638102444440243028923064531618719041600756898720	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	5188548017842198318313522523308764508271242973277563447008160477969325913040	368	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12138610705214129690679577776814058028814602546943740362672330328112549674300	368	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	83794424771231914422926600045027168336775184406063300605865116134602801852895	368	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	109112538253089283211650573452950536669021778137209507752378777374176468169891	327	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	15304251624410551271628715666693610554053522012292952569727742434975439776820	327	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	7983101945305385757483750880556802742881232613190804523169904021016777752160	327	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	81712519885080219157964064765309595488771432975375657820663392152839241346748	369	UVM_INFO @ 10294.450904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	96537043260825271678055178008082988671545905143531849386502520667285316103152	369	UVM_INFO @ 10326.610676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	112807839763901036345282278949324965807529858499757091451885341891325783902341	341	UVM_INFO @ 6929.615770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	11174814339026709242751096036801858086521029265492364670581496444895936090223	327	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	93286860954134910440089595381940100158603842156837617917800966820508129216580	328	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	98465978833455198356306286364548307587886726168346593359677667197783938891324	325	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				2 test runs
	chip_sw_otp_ctrl_escalation	22913671035950937457562268578290406545309533167407423231576305953734415368532	316	UVM_ERROR @ 3380.523438 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3380.523438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	114973143384446093829017347675932827062060487934216918906285760067100210727370	312	UVM_ERROR @ 2901.353736 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2901.353736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				2 test runs
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	75136135718947315199688549690909381525852615314015330160414526168904393443046	327	UVM_ERROR @ 10290.068000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 10290.068000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	30256706730997426858876443790539485027907534219137704257493595254444581754747	325	UVM_ERROR @ 6840.747000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 6840.747000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	94295341248486969852309853519628991467493215412077935174299294511235715364678	313	UVM_ERROR @ 3090.594608 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3090.594608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	50724537122438859258459101139072402997093099223529767454566637841040422313658	315	UVM_ERROR @ 5142.100151 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 5142.100151 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				2 test runs
	chip_sw_hmac_oneshot	81520580827744563833367121825195630276980498864993314187488701598552088829640	310	UVM_INFO @ 12026.881165 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_hmac_multistream	12577495510176153112830984950742926933060574433664751257163611253574592512189	310	UVM_INFO @ 12018.539413 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18592541184983295009362621358371353148001569377859693417197890910072617834054	362	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	112567614088629400518852176403376451870309054244285293388128219709438982412985	326	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	4335061439747174981186685337014141211761192136456184305174279177633462153843	365	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	22343066720874299386936316148059731827736477206987650571018341338421984716886	327	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	110608542927803456202349052086446874720735782433391270372032138025220176533716	301	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	21714521788520110327350676896637016479701136521216938366768087223789567457017	327	UVM_INFO @ 2722.579835 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	25704347698119811848095248696077390512478786870126275253947899851443379710042	309	UVM_INFO @ 2536.783242 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	35106532443575821563273211980483730198608506277030379427586497096598484107691	342	UVM_INFO @ 7124.713600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	99465295835623889994278853283542014252901258468872328230918008167483603002946	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	102680656277681838566411548757273747953501288109367006965783813221089388534876	303	UVM_ERROR @ 2320.664371 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 2320.664371 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'				1 test run
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	108447682699304247157906793031111567618860858086644404764421606273872849394751	341	UVM_ERROR @ 7303.152526 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 7303.152526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	56129298572489807578451250178649543369083851493894213204766961712686453637538	332	UVM_INFO @ 34923.974015 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	78320360605241423328521949502285634165750733429368630610524326041975864206512	307	UVM_INFO @ 3164.946528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	56570300872137917161450099783652290797460517159174597546533664532867263073453	308	UVM_INFO @ 2960.941150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	101856813265526175113691775035096001561009077757048405877773962977342523820323	None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	48907057055244698535564140604333583993632978577971442519449061980120776198436	343	UVM_INFO @ 3783.965818 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	98198743289328955905619927800893694894861438469594920892801831689956839086336	267	UVM_INFO @ 7443.116907 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [] vs [*]) Major alert did not match expectation.				1 test run
	chip_sw_rv_core_ibex_lockstep_glitch	69188647110645091923239752447288663019764785178284514583133940542461359009387	330	UVM_INFO @ 2786.268944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_idle_load	110656660074094920182595053517357647022349048267777291108038013471634447374572	312	UVM_INFO @ 3114.283000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_sleep_load	67361680531502563557329528372177294227589468629762291094838640368006823577971	318	UVM_INFO @ 3458.269000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	112574993971202605583659309748794256573297478196172227687442889682763654129954	327	UVM_INFO @ 9788.907061 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	17558286514389591875038743567455782892635624951010942202806733350131672456736	272	UVM_INFO @ 10010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	83561531605161995083043024083534867663038540714566346359905393505233341386421	325	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	45705652689544996371704529352403182854107989988125112770233155751558314504684	326	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_no_meas	73455550541116767953416669927457714212676838827742436836095224247926897182080	319	UVM_INFO @ 18473.909613 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	51689692771488072091904328934220236102093474208589553131913583680272570389947	327	UVM_ERROR @ 4643.455536 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4643.455536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---