Simulation Results: clkmgr

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.80 %
  • code
  • 98.13 %
  • assert
  • 95.20 %
  • func
  • 85.08 %
  • line
  • 99.00 %
  • branch
  • 98.69 %
  • cond
  • 93.78 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.780s 51.878us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.950s 20.527us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.850s 41.741us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.550s 418.363us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.330s 64.678us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.990s 82.643us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.850s 41.741us 1 1 100.00
clkmgr_csr_aliasing 1.330s 64.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.780s 15.463us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.700s 25.235us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.840s 80.012us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.630s 16.666us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.780s 51.878us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 3.830s 682.850us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.710s 257.132us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 3.830s 682.850us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 10.870s 3947.456us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.860s 87.281us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.200s 52.353us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.200s 52.353us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.950s 20.527us 1 1 100.00
clkmgr_csr_rw 0.850s 41.741us 1 1 100.00
clkmgr_csr_aliasing 1.330s 64.678us 1 1 100.00
clkmgr_same_csr_outstanding 1.520s 97.885us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.950s 20.527us 1 1 100.00
clkmgr_csr_rw 0.850s 41.741us 1 1 100.00
clkmgr_csr_aliasing 1.330s 64.678us 1 1 100.00
clkmgr_same_csr_outstanding 1.520s 97.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.780s 8.810us 0 1 0.00
clkmgr_tl_intg_err 2.330s 425.156us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 99.808us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 99.808us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 99.808us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 99.808us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.890s 107.365us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.330s 425.156us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 3.830s 682.850us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.710s 257.132us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 99.808us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.760s 20.312us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.900s 24.163us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.940s 39.491us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.750s 51.542us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.800s 22.996us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.850s 41.741us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.780s 8.810us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.850s 41.741us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.850s 41.741us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.780s 8.810us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.020s 391.386us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 27.660s 4547.414us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 114636197662862327088550726233241840673134658740624507211731906223303611021869 79
UVM_INFO @ 8810167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---