Simulation Results: edn/edn0

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.98 %
  • code
  • 79.67 %
  • assert
  • 96.10 %
  • func
  • 79.17 %
  • line
  • 97.34 %
  • branch
  • 90.24 %
  • cond
  • 84.97 %
  • toggle
  • 75.24 %
  • FSM
  • 50.54 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.960s 18.214us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.730s 46.710us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.860s 51.836us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.530s 293.215us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.430s 49.119us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.210s 150.697us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.860s 51.836us 1 1 100.00
edn_csr_aliasing 1.430s 49.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.320s 65.842us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.320s 65.842us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.320s 65.842us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.920s 27.093us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.250s 61.012us 1 1 100.00
errs 1 1 100.00
edn_err 0.960s 85.557us 1 1 100.00
disable 2 2 100.00
edn_disable 1.020s 21.131us 1 1 100.00
edn_disable_auto_req_mode 1.050s 96.449us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.190s 118.450us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.970s 15.401us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.150s 16.632us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.350s 157.274us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.350s 157.274us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.730s 46.710us 1 1 100.00
edn_csr_rw 0.860s 51.836us 1 1 100.00
edn_csr_aliasing 1.430s 49.119us 1 1 100.00
edn_same_csr_outstanding 0.920s 52.037us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.730s 46.710us 1 1 100.00
edn_csr_rw 0.860s 51.836us 1 1 100.00
edn_csr_aliasing 1.430s 49.119us 1 1 100.00
edn_same_csr_outstanding 0.920s 52.037us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.720s 6863.786us 1 1 100.00
edn_tl_intg_err 1.230s 60.529us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 17.226us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.250s 61.012us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.720s 6863.786us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.720s 6863.786us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.720s 6863.786us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.720s 6863.786us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.250s 61.012us 1 1 100.00
edn_sec_cm 6.720s 6863.786us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.250s 61.012us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.230s 60.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 23.950s 2904.978us 1 1 100.00