Simulation Results: edn/edn1

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.11 %
  • code
  • 82.36 %
  • assert
  • 97.14 %
  • func
  • 75.84 %
  • line
  • 98.18 %
  • branch
  • 93.07 %
  • cond
  • 86.31 %
  • toggle
  • 86.52 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 32.095us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.750s 28.000us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 49.566us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.740s 291.614us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.020s 240.420us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.060s 384.756us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 49.566us 1 1 100.00
edn_csr_aliasing 1.020s 240.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.060s 84.642us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.060s 84.642us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.060s 84.642us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.740s 22.106us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.820s 34.719us 1 1 100.00
errs 1 1 100.00
edn_err 0.880s 21.296us 1 1 100.00
disable 2 2 100.00
edn_disable 0.830s 16.357us 1 1 100.00
edn_disable_auto_req_mode 0.960s 192.023us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.620s 107.321us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.720s 21.644us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.800s 18.390us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.490s 55.068us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.490s 55.068us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.750s 28.000us 1 1 100.00
edn_csr_rw 0.790s 49.566us 1 1 100.00
edn_csr_aliasing 1.020s 240.420us 1 1 100.00
edn_same_csr_outstanding 1.160s 42.452us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.750s 28.000us 1 1 100.00
edn_csr_rw 0.790s 49.566us 1 1 100.00
edn_csr_aliasing 1.020s 240.420us 1 1 100.00
edn_same_csr_outstanding 1.160s 42.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.090s 673.065us 1 1 100.00
edn_tl_intg_err 1.600s 79.926us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.950s 23.927us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.820s 34.719us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.090s 673.065us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.090s 673.065us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.090s 673.065us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.090s 673.065us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.820s 34.719us 1 1 100.00
edn_sec_cm 2.090s 673.065us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.820s 34.719us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.600s 79.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 36.060s 2328.619us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 36269785590507531194534871302886273246393479680942083068804174775314416894869 189
UVM_INFO @ 2328619249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---