Simulation Results: entropy_src/rng_4bits

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.36 %
  • code
  • 88.94 %
  • assert
  • 84.56 %
  • func
  • 49.58 %
  • block
  • 94.56 %
  • line
  • 97.24 %
  • branch
  • 86.86 %
  • toggle
  • 75.84 %
  • FSM
  • 95.83 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 72.618us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 74.959us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 28.627us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 4.000s 84.833us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 354.460us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 11.007us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 28.627us 1 1 100.00
entropy_src_csr_aliasing 4.000s 354.460us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 72.618us 1 1 100.00
entropy_src_rng 16.000s 13481.942us 1 1 100.00
entropy_src_fw_ov 28.000s 14259.496us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 28.000s 14259.496us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 16.000s 13481.942us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 47.000s 14516.743us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 16.000s 13481.942us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 16.000s 13481.942us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 16.000s 13481.942us 1 1 100.00
entropy_src_intr 12.000s 8360.058us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 16.000s 13481.942us 1 1 100.00
entropy_src_functional_alerts 4.000s 343.478us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 53.000s 13621.479us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 113.173us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 84.594us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 44.969us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 18.575us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 420.144us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 420.144us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 74.959us 1 1 100.00
entropy_src_csr_rw 1.000s 28.627us 1 1 100.00
entropy_src_csr_aliasing 4.000s 354.460us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 109.243us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 74.959us 1 1 100.00
entropy_src_csr_rw 1.000s 28.627us 1 1 100.00
entropy_src_csr_aliasing 4.000s 354.460us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 109.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 1.000s 81.328us 1 1 100.00
entropy_src_tl_intg_err 4.000s 207.642us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 16.000s 13481.942us 1 1 100.00
entropy_src_cfg_regwen 2.000s 16.295us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 16.000s 13481.942us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 16.000s 13481.942us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 16.000s 13481.942us 1 1 100.00
entropy_src_fw_ov 28.000s 14259.496us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 113.173us 1 1 100.00
entropy_src_sec_cm 1.000s 81.328us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 113.173us 1 1 100.00
entropy_src_sec_cm 1.000s 81.328us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 16.000s 13481.942us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 113.173us 1 1 100.00
entropy_src_sec_cm 1.000s 81.328us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 113.173us 1 1 100.00
entropy_src_sec_cm 1.000s 81.328us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 113.173us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 343.478us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 207.642us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 182.000s 13015.651us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 11.000s 651.308us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 103594499647482161390698731130400647521289856885517275222960947090628944878898 271
UVM_INFO @ 651308483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 71160531736819995742866329834900183054365343053874728184725679412860824966935 113
UVM_INFO @ 11007483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---