Simulation Results: flash_ctrl

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.59 %
  • code
  • 93.77 %
  • assert
  • 97.01 %
  • func
  • 95.98 %
  • line
  • 95.94 %
  • branch
  • 97.12 %
  • cond
  • 93.60 %
  • toggle
  • 97.16 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 23.680s 24.208us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 12.150s 17.188us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 14.650s 34.325us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.860s 722.488us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 30.780s 1740.080us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 25.470s 2974.737us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.660s 57.469us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.860s 722.488us 1 1 100.00
flash_ctrl_csr_aliasing 25.470s 2974.737us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.320s 30.444us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.530s 18.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 12.270s 128.059us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 38.610s 129.319us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1316.030s 426810.876us 1 1 100.00
flash_ctrl_hw_rma_reset 587.590s 420380.550us 1 1 100.00
flash_ctrl_lcmgr_intg 10.180s 43.525us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1219.720s 599713.950us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 216.020s 8192.044us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.560s 23.869us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1970.230s 393333.149us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 45.140s 107.459us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.090s 49.939us 1 1 100.00
flash_ctrl_rw_evict_all_en 18.320s 189.144us 1 1 100.00
flash_ctrl_re_evict 16.500s 134.298us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 23.240s 129.502us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 23.240s 129.502us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 100.310s 11250.052us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 12.250s 144.619us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 261.650s 400.674us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 332.020s 13112.626us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 333.780s 8074.109us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 864.500s 3520.941us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.190s 25.216us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 129.500s 4511.155us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.080s 31.707us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.570s 17.724us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 518.400s 1286.347us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 50.340s 2293.569us 1 1 100.00
flash_ctrl_otp_reset 62.840s 250.543us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1316.030s 426810.876us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 116.170s 2286.251us 1 1 100.00
flash_ctrl_intr_wr 45.950s 2307.442us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 175.290s 11721.675us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 146.440s 380999.585us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 50.400s 3974.801us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 35.600s 1099.152us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 14.120s 44.928us 1 1 100.00
flash_ctrl_ro_derr 99.800s 677.186us 1 1 100.00
flash_ctrl_rw_derr 103.790s 898.011us 1 1 100.00
flash_ctrl_derr_detect 113.050s 1268.932us 1 1 100.00
flash_ctrl_integrity 498.980s 12124.263us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 12.660s 84.214us 1 1 100.00
flash_ctrl_ro_serr 88.260s 743.881us 1 1 100.00
flash_ctrl_rw_serr 116.530s 9357.474us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 63.540s 982.867us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 56.800s 1842.909us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 100.320s 4802.917us 1 1 100.00
flash_ctrl_write_word_sweep 7.190s 75.047us 1 1 100.00
flash_ctrl_read_word_sweep 8.860s 25.175us 1 1 100.00
flash_ctrl_ro 83.750s 1019.198us 1 1 100.00
flash_ctrl_rw 487.860s 21976.094us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.440s 976.330us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 900.520s 103042.848us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 30.180s 10060.701us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.330s 78.320us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 8.820s 16.946us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 12.090s 127.307us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 12.090s 127.307us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.650s 34.325us 1 1 100.00
flash_ctrl_csr_rw 9.860s 722.488us 1 1 100.00
flash_ctrl_csr_aliasing 25.470s 2974.737us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.540s 436.884us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.650s 34.325us 1 1 100.00
flash_ctrl_csr_rw 9.860s 722.488us 1 1 100.00
flash_ctrl_csr_aliasing 25.470s 2974.737us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.540s 436.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 34.680s 71.737us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 34.680s 71.737us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 34.680s 71.737us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 34.680s 71.737us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 25.110s 156.523us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1778.680s 2096.789us 1 1 100.00
flash_ctrl_tl_intg_err 411.010s 9109.202us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 411.010s 9109.202us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 411.010s 9109.202us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 22.160s 194.667us 1 1 100.00
flash_ctrl_wr_intg 6.710s 47.087us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 23.680s 24.208us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 62.840s 250.543us 1 1 100.00
flash_ctrl_disable 10.080s 31.707us 1 1 100.00
flash_ctrl_sec_info_access 38.620s 5029.733us 1 1 100.00
flash_ctrl_connect 7.570s 17.724us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.790s 37.652us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.860s 722.488us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 34.680s 71.737us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.860s 722.488us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 34.680s 71.737us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.860s 722.488us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 34.680s 71.737us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.080s 31.707us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 22.160s 194.667us 1 1 100.00
flash_ctrl_access_after_disable 5.860s 26.613us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.650s 38.284us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.080s 31.707us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 12.250s 144.619us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 487.860s 21976.094us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 116.530s 9357.474us 1 1 100.00
flash_ctrl_rw_derr 103.790s 898.011us 1 1 100.00
flash_ctrl_integrity 498.980s 12124.263us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1316.030s 426810.876us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1778.680s 2096.789us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1778.680s 2096.789us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1778.680s 2096.789us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1778.680s 2096.789us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.070s 870.734us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.360s 39.025us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 8.570s 24.094us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1778.680s 2096.789us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1778.680s 2096.789us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1778.680s 2096.789us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 22.900s 44.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 193.480s 1169.407us 1 1 100.00