Simulation Results: hmac

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.02 %
  • code
  • 97.29 %
  • assert
  • 97.80 %
  • func
  • 41.98 %
  • line
  • 99.64 %
  • branch
  • 99.34 %
  • cond
  • 96.29 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.630s 2899.951us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.740s 42.170us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.750s 19.597us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.120s 1285.313us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.600s 107.951us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 121.920s 16989.254us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.750s 19.597us 1 1 100.00
hmac_csr_aliasing 3.600s 107.951us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 15.040s 3136.296us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 66.920s 3134.045us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 206.360s 6975.107us 1 1 100.00
hmac_test_sha384_vectors 429.790s 14445.982us 1 1 100.00
hmac_test_sha512_vectors 382.690s 98093.282us 1 1 100.00
hmac_test_hmac256_vectors 7.300s 475.717us 1 1 100.00
hmac_test_hmac384_vectors 12.480s 3037.701us 1 1 100.00
hmac_test_hmac512_vectors 8.660s 267.257us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 10.830s 217.885us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 226.090s 3518.997us 1 1 100.00
error 1 1 100.00
hmac_error 50.930s 5111.436us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 5.030s 104.560us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.630s 2899.951us 1 1 100.00
hmac_long_msg 15.040s 3136.296us 1 1 100.00
hmac_back_pressure 66.920s 3134.045us 1 1 100.00
hmac_datapath_stress 226.090s 3518.997us 1 1 100.00
hmac_burst_wr 10.830s 217.885us 1 1 100.00
hmac_stress_all 16.880s 457.006us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.630s 2899.951us 1 1 100.00
hmac_long_msg 15.040s 3136.296us 1 1 100.00
hmac_back_pressure 66.920s 3134.045us 1 1 100.00
hmac_datapath_stress 226.090s 3518.997us 1 1 100.00
hmac_wipe_secret 5.030s 104.560us 1 1 100.00
hmac_test_sha256_vectors 206.360s 6975.107us 1 1 100.00
hmac_test_sha384_vectors 429.790s 14445.982us 1 1 100.00
hmac_test_sha512_vectors 382.690s 98093.282us 1 1 100.00
hmac_test_hmac256_vectors 7.300s 475.717us 1 1 100.00
hmac_test_hmac384_vectors 12.480s 3037.701us 1 1 100.00
hmac_test_hmac512_vectors 8.660s 267.257us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.630s 2899.951us 1 1 100.00
hmac_long_msg 15.040s 3136.296us 1 1 100.00
hmac_back_pressure 66.920s 3134.045us 1 1 100.00
hmac_datapath_stress 226.090s 3518.997us 1 1 100.00
hmac_burst_wr 10.830s 217.885us 1 1 100.00
hmac_error 50.930s 5111.436us 1 1 100.00
hmac_wipe_secret 5.030s 104.560us 1 1 100.00
hmac_test_sha256_vectors 206.360s 6975.107us 1 1 100.00
hmac_test_sha384_vectors 429.790s 14445.982us 1 1 100.00
hmac_test_sha512_vectors 382.690s 98093.282us 1 1 100.00
hmac_test_hmac256_vectors 7.300s 475.717us 1 1 100.00
hmac_test_hmac384_vectors 12.480s 3037.701us 1 1 100.00
hmac_test_hmac512_vectors 8.660s 267.257us 1 1 100.00
hmac_stress_all 16.880s 457.006us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 16.880s 457.006us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.620s 48.995us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.860s 13.846us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.680s 278.957us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.680s 278.957us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.740s 42.170us 1 1 100.00
hmac_csr_rw 0.750s 19.597us 1 1 100.00
hmac_csr_aliasing 3.600s 107.951us 1 1 100.00
hmac_same_csr_outstanding 1.750s 78.903us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.740s 42.170us 1 1 100.00
hmac_csr_rw 0.750s 19.597us 1 1 100.00
hmac_csr_aliasing 3.600s 107.951us 1 1 100.00
hmac_same_csr_outstanding 1.750s 78.903us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.240s 257.089us 1 1 100.00
hmac_tl_intg_err 3.940s 285.160us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.940s 285.160us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.630s 2899.951us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.750s 345.537us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 96.370s 10513.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.900s 228.293us 1 1 100.00