Simulation Results

Simulation Results: i2c

08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
87.23 %

code
82.19 %

assert
97.46 %

func
82.03 %

line
96.66 %

branch
92.90 %

cond
87.07 %

toggle
89.66 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		92.68%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	36.580s	4258.722us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.030s	1785.085us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.790s	19.773us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.790s	29.159us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	1.990s	1086.446us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.880s	75.180us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.020s	57.942us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.790s	29.159us	1	1	100.00
	i2c_csr_aliasing	1.880s	75.180us	1	1	100.00

38/41 passed

92.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.750s	3.592us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	94.890s	9107.474us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	22.230s	13917.374us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.800s	18.615us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	48.030s	7539.680us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	56.960s	4248.131us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.950s	103.241us	1	1	100.00
	i2c_host_fifo_fmt_empty	17.260s	982.846us	1	1	100.00
	i2c_host_fifo_reset_rx	2.910s	1430.475us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	57.110s	10938.195us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	9.550s	709.730us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.880s	83.991us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.430s	2420.569us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	911.260s	65952.476us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.810s	2817.333us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	5.140s	1089.472us	1	1	100.00
	i2c_target_intr_smoke	3.830s	2802.487us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.860s	221.491us	1	1	100.00
	i2c_target_fifo_reset_tx	1.100s	246.498us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	69.400s	47230.988us	1	1	100.00
	i2c_target_stress_rd	5.140s	1089.472us	1	1	100.00
	i2c_target_intr_stress_wr	11.040s	8921.045us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.620s	12597.950us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	5.790s	3241.696us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.130s	681.220us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	10.340s	10031.291us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.300s	551.760us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.050s	187.845us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	22.230s	13917.374us	1	1	100.00
	i2c_host_perf_precise	268.750s	5901.260us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	9.550s	709.730us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.930s	320.294us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.600s	5928.368us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.150s	528.829us	1	1	100.00
	i2c_target_nack_txstretch	1.760s	1607.976us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	2.800s	2294.285us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.630s	670.536us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.790s	27.069us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.990s	61.007us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.160s	79.127us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.160s	79.127us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.790s	19.773us	1	1	100.00
	i2c_csr_rw	0.790s	29.159us	1	1	100.00
	i2c_csr_aliasing	1.880s	75.180us	1	1	100.00
	i2c_same_csr_outstanding	1.190s	58.229us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.790s	19.773us	1	1	100.00
	i2c_csr_rw	0.790s	29.159us	1	1	100.00
	i2c_csr_aliasing	1.880s	75.180us	1	1	100.00
	i2c_same_csr_outstanding	1.190s	58.229us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.120s	254.889us	1	1	100.00
	i2c_sec_cm	0.810s	365.071us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.120s	254.889us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	3.740s	1014.691us	1
target_error_intr				1
	i2c_target_unexp_stop	1.030s	128.060us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	28.380s	1062.735us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	76078740839522707705605992411527160310550221229345918843567122076737043230727	80	UVM_INFO @ 3591568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	23796285194683940956584520756201263488616166376231179073019697830682812425375	84	UVM_INFO @ 2420569428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	42716203292235519776793562793388576987992756924865963004524382964070111813056	78	UVM_INFO @ 128059540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	102003266201644755101775371734169356216405111056954959306075835409376926002807	79	UVM_INFO @ 10031291403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	103196236577258974501581165576340998597532852275977870460012618414223481605351	84	UVM_INFO @ 1014691250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1199) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.				1 test run
	i2c_target_stress_all_with_rand_reset	78831764320748606357839961422891072885148685736108767340732017713532934022967	95	UVM_INFO @ 1062734790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---