Simulation Results: kmac/unmasked

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.99 %
  • code
  • 87.97 %
  • assert
  • 98.50 %
  • func
  • 92.50 %
  • line
  • 97.28 %
  • branch
  • 95.39 %
  • cond
  • 93.65 %
  • toggle
  • 99.83 %
  • FSM
  • 53.72 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 30.040s 5087.957us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.190s 112.100us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.400s 118.394us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 9.040s 2983.451us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.910s 224.576us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.670s 102.479us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.400s 118.394us 1 1 100.00
kmac_csr_aliasing 3.910s 224.576us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.760s 16.496us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.280s 49.126us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2340.580s 98151.071us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 485.380s 22172.956us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 32.960s 3089.708us 1 1 100.00
kmac_test_vectors_sha3_256 1934.240s 169644.520us 1 1 100.00
kmac_test_vectors_sha3_384 852.910s 54478.133us 1 1 100.00
kmac_test_vectors_sha3_512 592.560s 16587.291us 1 1 100.00
kmac_test_vectors_shake_128 103.060s 7591.963us 1 1 100.00
kmac_test_vectors_shake_256 94.770s 44588.033us 1 1 100.00
kmac_test_vectors_kmac 2.470s 87.643us 1 1 100.00
kmac_test_vectors_kmac_xof 2.130s 162.182us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 295.060s 20275.637us 1 1 100.00
app 1 1 100.00
kmac_app 117.460s 32126.194us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 257.470s 59608.432us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 201.870s 16496.887us 1 1 100.00
error 1 1 100.00
kmac_error 92.650s 1773.439us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 2.070s 954.667us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 94.270s 10079.915us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 9.390s 1198.063us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 3.070s 79.653us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 62.890s 15744.323us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 5.570s 97.357us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 1031.170s 18240.281us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 1.040s 34.824us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.130s 14.643us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.920s 89.831us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.920s 89.831us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.190s 112.100us 1 1 100.00
kmac_csr_rw 1.400s 118.394us 1 1 100.00
kmac_csr_aliasing 3.910s 224.576us 1 1 100.00
kmac_same_csr_outstanding 1.320s 240.305us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.190s 112.100us 1 1 100.00
kmac_csr_rw 1.400s 118.394us 1 1 100.00
kmac_csr_aliasing 3.910s 224.576us 1 1 100.00
kmac_same_csr_outstanding 1.320s 240.305us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.320s 44.904us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.320s 44.904us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.320s 44.904us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.320s 44.904us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.690s 453.997us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 25.020s 5665.707us 1 1 100.00
kmac_tl_intg_err 2.570s 453.729us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.570s 453.729us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 5.570s 97.357us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 30.040s 5087.957us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 295.060s 20275.637us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.320s 44.904us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 25.020s 5665.707us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 25.020s 5665.707us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 25.020s 5665.707us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 30.040s 5087.957us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 5.570s 97.357us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 25.020s 5665.707us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 123.690s 13228.538us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 30.040s 5087.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 168.780s 12130.957us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) 1 test run
kmac_sideload_invalid 48103950628842849647388431180385263732635243185192652374705562632287016088380 89
UVM_INFO @ 10079914909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---