Simulation Results: lc_ctrl/volatile_unlock_disabled

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.78 %
  • code
  • 84.09 %
  • assert
  • 94.13 %
  • func
  • 94.13 %
  • line
  • 97.15 %
  • branch
  • 93.70 %
  • cond
  • 79.86 %
  • toggle
  • 86.20 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.310s 410.533us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.060s 18.585us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.880s 24.401us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.600s 29.257us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 79.713us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.290s 24.756us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.880s 24.401us 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 79.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.090s 161.352us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 14.160s 1317.881us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.960s 13.331us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.810s 325.811us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.010s 281.313us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.430s 375.119us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.010s 281.313us 1 1 100.00
lc_ctrl_prog_failure 2.810s 325.811us 1 1 100.00
lc_ctrl_errors 5.430s 375.119us 1 1 100.00
lc_ctrl_security_escalation 6.950s 574.248us 1 1 100.00
lc_ctrl_jtag_state_failure 15.960s 10922.417us 1 1 100.00
lc_ctrl_jtag_prog_failure 11.100s 515.919us 1 1 100.00
lc_ctrl_jtag_errors 18.070s 1447.995us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 7.010s 970.131us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.690s 639.582us 1 1 100.00
lc_ctrl_jtag_prog_failure 11.100s 515.919us 1 1 100.00
lc_ctrl_jtag_errors 18.070s 1447.995us 1 1 100.00
lc_ctrl_jtag_access 9.230s 853.529us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.570s 1827.907us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.950s 322.695us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.210s 71.189us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.520s 2132.919us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.050s 1052.950us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.610s 52.435us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.670s 48.664us 1 1 100.00
lc_ctrl_jtag_alert_test 1.610s 58.208us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.400s 1989.531us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.990s 16.592us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 4.340s 184.788us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.320s 20.835us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.300s 445.973us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.300s 445.973us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.060s 18.585us 1 1 100.00
lc_ctrl_csr_rw 0.880s 24.401us 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 79.713us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.320s 47.314us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.060s 18.585us 1 1 100.00
lc_ctrl_csr_rw 0.880s 24.401us 1 1 100.00
lc_ctrl_csr_aliasing 1.510s 79.713us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.320s 47.314us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.290s 159.172us 1 1 100.00
lc_ctrl_tl_intg_err 2.660s 438.555us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.660s 438.555us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 14.160s 1317.881us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.010s 281.313us 1 1 100.00
lc_ctrl_sec_cm 6.290s 159.172us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.010s 281.313us 1 1 100.00
lc_ctrl_sec_cm 6.290s 159.172us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.010s 281.313us 1 1 100.00
lc_ctrl_sec_cm 6.290s 159.172us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.010s 281.313us 1 1 100.00
lc_ctrl_sec_cm 6.290s 159.172us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.010s 281.313us 1 1 100.00
lc_ctrl_sec_cm 6.290s 159.172us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.010s 281.313us 1 1 100.00
lc_ctrl_sec_cm 6.290s 159.172us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.010s 281.313us 1 1 100.00
lc_ctrl_sec_cm 6.290s 159.172us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.010s 281.313us 1 1 100.00
lc_ctrl_sec_cm 6.290s 159.172us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.950s 574.248us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.090s 161.352us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.690s 639.582us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.650s 470.797us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.650s 470.797us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.130s 333.347us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.190s 1577.392us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.190s 1577.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 5.140s 379.772us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 25261884857671776561300893911005688656081554007170959154446660750978687387622 200
UVM_INFO @ 379771964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---