Simulation Results: lc_ctrl/volatile_unlock_enabled

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.75 %
  • code
  • 84.00 %
  • assert
  • 94.83 %
  • func
  • 93.42 %
  • line
  • 97.13 %
  • branch
  • 93.37 %
  • cond
  • 78.78 %
  • toggle
  • 89.06 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.020s 50.355us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.730s 96.891us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.970s 19.681us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.150s 33.511us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 67.338us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.940s 22.758us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.970s 19.681us 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 67.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.470s 428.426us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.340s 204.625us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.060s 13.302us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.780s 335.467us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 11.120s 811.493us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.970s 1581.855us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 11.120s 811.493us 1 1 100.00
lc_ctrl_prog_failure 2.780s 335.467us 1 1 100.00
lc_ctrl_errors 7.970s 1581.855us 1 1 100.00
lc_ctrl_security_escalation 5.730s 1016.168us 1 1 100.00
lc_ctrl_jtag_state_failure 16.500s 2209.838us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.920s 2494.975us 1 1 100.00
lc_ctrl_jtag_errors 52.710s 22539.669us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.760s 1357.087us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.980s 1722.264us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.920s 2494.975us 1 1 100.00
lc_ctrl_jtag_errors 52.710s 22539.669us 1 1 100.00
lc_ctrl_jtag_access 5.790s 230.322us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.010s 2711.597us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.330s 78.504us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.890s 278.428us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 17.330s 4513.203us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.910s 698.448us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.870s 29.695us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.400s 57.903us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 109.629us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 13.910s 1739.372us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.910s 16.092us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 160.130s 32265.720us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.420s 24.806us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.210s 65.856us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.210s 65.856us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.730s 96.891us 1 1 100.00
lc_ctrl_csr_rw 0.970s 19.681us 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 67.338us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 45.036us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.730s 96.891us 1 1 100.00
lc_ctrl_csr_rw 0.970s 19.681us 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 67.338us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 45.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.380s 125.400us 1 1 100.00
lc_ctrl_tl_intg_err 1.300s 68.978us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.300s 68.978us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.340s 204.625us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 11.120s 811.493us 1 1 100.00
lc_ctrl_sec_cm 5.380s 125.400us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 11.120s 811.493us 1 1 100.00
lc_ctrl_sec_cm 5.380s 125.400us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.120s 811.493us 1 1 100.00
lc_ctrl_sec_cm 5.380s 125.400us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.120s 811.493us 1 1 100.00
lc_ctrl_sec_cm 5.380s 125.400us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 11.120s 811.493us 1 1 100.00
lc_ctrl_sec_cm 5.380s 125.400us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.120s 811.493us 1 1 100.00
lc_ctrl_sec_cm 5.380s 125.400us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.120s 811.493us 1 1 100.00
lc_ctrl_sec_cm 5.380s 125.400us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 11.120s 811.493us 1 1 100.00
lc_ctrl_sec_cm 5.380s 125.400us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.730s 1016.168us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.470s 428.426us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.980s 1722.264us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.050s 484.122us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.050s 484.122us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.910s 293.309us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.700s 242.793us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.700s 242.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 94.320s 8984.658us 1 1 100.00