Simulation Results: pattgen

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.69 %
  • code
  • 98.87 %
  • assert
  • 98.78 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
81.82%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 92.346us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 3.000s 54.906us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 12.676us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 65.848us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 42.307us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 45.206us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 12.676us 1 1 100.00
pattgen_csr_aliasing 1.000s 42.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 1024.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 30.000s 7758.122us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 62.324us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 7276.000s 1516303.659us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 2.000s 14.219us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 12.738us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 50.742us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 50.742us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 3.000s 54.906us 1 1 100.00
pattgen_csr_rw 1.000s 12.676us 1 1 100.00
pattgen_csr_aliasing 1.000s 42.307us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 134.188us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 3.000s 54.906us 1 1 100.00
pattgen_csr_rw 1.000s 12.676us 1 1 100.00
pattgen_csr_aliasing 1.000s 42.307us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 134.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 2.000s 241.768us 1 1 100.00
pattgen_sec_cm 1.000s 222.666us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 241.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 35.000s 3088.627us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 106.330us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pattgen_perf 18691811539613284577875892704940237272309264694147975863342978181121338385650 99
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
pattgen_stress_all_with_rand_reset 60306538102531280551749778267517158391305800221984931725185461657877973651165 236
UVM_ERROR @ 1412041515 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1412041515 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 1412072766 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: 1 test run
pattgen_stress_all 83436432291771052842742018962598102504997968268639332684842073138773767489727 147
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11070