Simulation Results: pwrmgr

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.50 %
  • code
  • 91.25 %
  • assert
  • 97.39 %
  • func
  • 97.86 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.62 %
  • toggle
  • 91.15 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
80.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.780s 30.256us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.890s 46.004us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.590s 19.286us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.640s 602.201us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.820s 21.936us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.010s 106.125us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.590s 19.286us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 21.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.750s 226.884us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.750s 226.884us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.990s 57.086us 1 1 100.00
pwrmgr_lowpower_invalid 0.630s 70.821us 1 1 100.00
reset 0 2 0.00
pwrmgr_reset 2.170s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.750s 42.303us 0 1 0.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 2.170s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.120s 251.897us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.860s 367.258us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 2.120s 1000.000us 0 1 0.00
stress_all 1 1 100.00
pwrmgr_stress_all 4.480s 2122.572us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.590s 59.661us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.070s 342.265us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.070s 342.265us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.890s 46.004us 1 1 100.00
pwrmgr_csr_rw 0.590s 19.286us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 21.936us 1 1 100.00
pwrmgr_same_csr_outstanding 0.740s 75.263us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.890s 46.004us 1 1 100.00
pwrmgr_csr_rw 0.590s 19.286us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 21.936us 1 1 100.00
pwrmgr_same_csr_outstanding 0.740s 75.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.230s 261.806us 1 1 100.00
pwrmgr_sec_cm 0.960s 484.901us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 0.960s 484.901us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 0.960s 484.901us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.230s 261.806us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.610s 1610.617us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 1.120s 251.897us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.730s 849.598us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.800s 157.740us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.620s 40.549us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 0.960s 484.901us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 0.960s 484.901us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 0.960s 484.901us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.580s 59.425us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.600s 59.374us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.840s 128.456us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 19.286us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 19.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.730s 523.164us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 2.900s 2163.613us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
pwrmgr_reset 89579974685680285614921819093368650880127995415030563867565824874170405467838 116
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 19788683997228405995137105701043637737342611388410716745793728631376422338880 125
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitResetPrep 1 test run
pwrmgr_reset_invalid 41297284010793424494530518229352529727201584003107824473388983189032272909767 89
UVM_INFO @ 42302887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---