Simulation Results: rom_ctrl/32kb

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.29 %
  • code
  • 97.71 %
  • assert
  • 97.53 %
  • func
  • 81.62 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.47 %
  • toggle
  • 99.36 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.130s 179.903us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.510s 298.887us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.750s 123.750us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.780s 535.307us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.210s 210.012us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.570s 233.842us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.750s 123.750us 1 1 100.00
rom_ctrl_csr_aliasing 3.210s 210.012us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.950s 533.688us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.660s 124.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.260s 135.860us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 9.230s 406.489us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.970s 299.253us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.130s 416.075us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.470s 416.918us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.470s 416.918us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.510s 298.887us 1 1 100.00
rom_ctrl_csr_rw 3.750s 123.750us 1 1 100.00
rom_ctrl_csr_aliasing 3.210s 210.012us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.120s 168.141us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.510s 298.887us 1 1 100.00
rom_ctrl_csr_rw 3.750s 123.750us 1 1 100.00
rom_ctrl_csr_aliasing 3.210s 210.012us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.120s 168.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 72.200s 2596.131us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.990s 1658.551us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 104.700s 378.630us 1 1 100.00
rom_ctrl_tl_intg_err 23.540s 586.671us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 104.700s 378.630us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 104.700s 378.630us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 72.200s 2596.131us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 72.200s 2596.131us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 72.200s 2596.131us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 72.200s 2596.131us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 72.200s 2596.131us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 104.700s 378.630us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 104.700s 378.630us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.130s 179.903us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.130s 179.903us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.130s 179.903us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.540s 586.671us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 72.200s 2596.131us 1 1 100.00
rom_ctrl_kmac_err_chk 7.970s 299.253us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 72.200s 2596.131us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 72.200s 2596.131us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 72.200s 2596.131us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.990s 1658.551us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 104.700s 378.630us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 291.400s 3314.964us 1 1 100.00