Simulation Results: rom_ctrl/64kb

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.78 %
  • code
  • 99.29 %
  • assert
  • 97.38 %
  • func
  • 96.66 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 97.62 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.870s 895.255us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.270s 550.885us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.180s 553.642us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.000s 212.717us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.890s 1276.824us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.710s 569.690us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.180s 553.642us 1 1 100.00
rom_ctrl_csr_aliasing 6.890s 1276.824us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.460s 1030.003us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.800s 289.261us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.080s 216.651us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 31.780s 2145.889us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 15.590s 390.912us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.000s 955.585us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.430s 325.590us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.430s 325.590us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.270s 550.885us 1 1 100.00
rom_ctrl_csr_rw 7.180s 553.642us 1 1 100.00
rom_ctrl_csr_aliasing 6.890s 1276.824us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.650s 1871.919us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.270s 550.885us 1 1 100.00
rom_ctrl_csr_rw 7.180s 553.642us 1 1 100.00
rom_ctrl_csr_aliasing 6.890s 1276.824us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.650s 1871.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 205.460s 12932.594us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.250s 4281.695us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 242.670s 564.550us 1 1 100.00
rom_ctrl_tl_intg_err 57.140s 623.532us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 242.670s 564.550us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 242.670s 564.550us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 205.460s 12932.594us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 205.460s 12932.594us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 205.460s 12932.594us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 205.460s 12932.594us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 205.460s 12932.594us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 242.670s 564.550us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 242.670s 564.550us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.870s 895.255us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.870s 895.255us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.870s 895.255us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 57.140s 623.532us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 205.460s 12932.594us 1 1 100.00
rom_ctrl_kmac_err_chk 15.590s 390.912us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 205.460s 12932.594us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 205.460s 12932.594us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 205.460s 12932.594us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.250s 4281.695us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 242.670s 564.550us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 288.280s 39277.161us 1 1 100.00