Simulation Results: rstmgr

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.53 %
  • code
  • 99.16 %
  • assert
  • 98.66 %
  • func
  • 94.78 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.12 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.400s 270.869us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.950s 93.320us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.960s 87.200us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.490s 280.246us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.830s 248.573us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.170s 155.027us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.960s 87.200us 1 1 100.00
rstmgr_csr_aliasing 1.830s 248.573us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.800s 199.776us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.580s 150.112us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.850s 94.191us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.550s 2109.039us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.550s 2109.039us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.550s 2109.039us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.550s 2109.039us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 0.770s 95.366us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.830s 58.999us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.490s 457.068us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.490s 457.068us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.950s 93.320us 1 1 100.00
rstmgr_csr_rw 0.960s 87.200us 1 1 100.00
rstmgr_csr_aliasing 1.830s 248.573us 1 1 100.00
rstmgr_same_csr_outstanding 1.090s 155.994us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.950s 93.320us 1 1 100.00
rstmgr_csr_rw 0.960s 87.200us 1 1 100.00
rstmgr_csr_aliasing 1.830s 248.573us 1 1 100.00
rstmgr_same_csr_outstanding 1.090s 155.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 20.490s 17716.538us 1 1 100.00
rstmgr_tl_intg_err 1.840s 482.360us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.490s 17716.538us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.490s 17716.538us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.840s 482.360us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.040s 111.953us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.590s 2680.973us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.000s 302.375us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.490s 17716.538us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.960s 87.200us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.960s 87.200us 1 1 100.00