Simulation Results: rv_timer

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.61 %
  • code
  • 99.81 %
  • assert
  • 98.09 %
  • func
  • 97.94 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 99.22 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.860s 166.085us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.630s 41.964us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.590s 34.362us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.820s 65.244us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.840s 28.099us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.780s 289.205us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.590s 34.362us 1 1 100.00
rv_timer_csr_aliasing 0.840s 28.099us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.800s 1199.736us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 3305.216us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 120.760s 104992.520us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 120.760s 104992.520us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.140s 206.434us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 41.440us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.610s 42.644us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.050s 89.945us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.050s 89.945us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 41.964us 1 1 100.00
rv_timer_csr_rw 0.590s 34.362us 1 1 100.00
rv_timer_csr_aliasing 0.840s 28.099us 1 1 100.00
rv_timer_same_csr_outstanding 0.780s 55.045us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 41.964us 1 1 100.00
rv_timer_csr_rw 0.590s 34.362us 1 1 100.00
rv_timer_csr_aliasing 0.840s 28.099us 1 1 100.00
rv_timer_same_csr_outstanding 0.780s 55.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.790s 65.238us 1 1 100.00
rv_timer_tl_intg_err 0.780s 60.931us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.780s 60.931us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.650s 16.910us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 1.150s 168.839us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 38.880s 23814.816us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 62650395674175036579005380609683154411153337716919154317474716512561755201817 75
UVM_INFO @ 168838876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 74543704130153254934853804747186778080452099233853667884260649400830808792507 75
UVM_INFO @ 1199735635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---