Simulation Results: spi_device/2p

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.80 %
  • code
  • 94.04 %
  • assert
  • 95.49 %
  • func
  • 61.86 %
  • line
  • 98.84 %
  • branch
  • 98.11 %
  • cond
  • 96.13 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 48.950s 96180.585us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.030s 25.510us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.050s 20.057us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 21.960s 6528.511us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 4.100s 218.589us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.320s 132.696us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.050s 20.057us 1 1 100.00
spi_device_csr_aliasing 4.100s 218.589us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.730s 19.289us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.610s 288.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.690s 27.066us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.120s 17.138us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.690s 39.535us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 6.810s 657.932us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 6.810s 657.932us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 4.330s 1520.254us 1 1 100.00
spi_device_tpm_sts_read 0.810s 34.450us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 9.260s 7844.882us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.120s 2843.713us 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.800s 736.101us 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.800s 736.101us 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.600s 306.744us 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.600s 306.744us 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.600s 306.744us 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.600s 306.744us 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.600s 306.744us 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 12.520s 10366.657us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.360s 11779.380us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.360s 11779.380us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.360s 11779.380us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 10.490s 1658.877us 1 1 100.00
spi_device_read_buffer_direct 2.590s 1753.233us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.360s 11779.380us 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 0.940s 82.314us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.290s 920.923us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.290s 920.923us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 123.950s 30588.426us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 48.950s 96180.585us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 161.570s 331935.737us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 0.810s 230.565us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.830s 43.885us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.770s 13.824us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.030s 157.782us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.030s 157.782us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.030s 25.510us 1 1 100.00
spi_device_csr_rw 1.050s 20.057us 1 1 100.00
spi_device_csr_aliasing 4.100s 218.589us 1 1 100.00
spi_device_same_csr_outstanding 3.240s 428.188us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.030s 25.510us 1 1 100.00
spi_device_csr_rw 1.050s 20.057us 1 1 100.00
spi_device_csr_aliasing 4.100s 218.589us 1 1 100.00
spi_device_same_csr_outstanding 3.240s 428.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.020s 144.115us 1 1 100.00
spi_device_tl_intg_err 15.290s 1048.286us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 15.290s 1048.286us 1 1 100.00