Simulation Results: spi_host

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.13 %
  • code
  • 95.03 %
  • assert
  • 95.27 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 40.000s 2356.788us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 19.833us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 19.953us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 379.903us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 19.599us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 22.310us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 19.953us 1 1 100.00
spi_host_csr_aliasing 2.000s 19.599us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 74.253us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 27.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 56.077us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 112.180us 1 1 100.00
spi_host_error_cmd 1.000s 52.664us 1 1 100.00
spi_host_event 18.000s 631.865us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 5.000s 386.172us 1 1 100.00
speed 1 1 100.00
spi_host_speed 5.000s 386.172us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 5.000s 386.172us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 236.000s 5282.766us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 4.000s 178.362us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 63.865us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 5.000s 386.172us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 5.000s 386.172us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 40.000s 2356.788us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 40.000s 2356.788us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 3.000s 140.888us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 611.940us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 62.000s 7211.993us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 1.000s 68.504us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 112.180us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 29.473us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 19.539us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 199.321us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 199.321us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.833us 1 1 100.00
spi_host_csr_rw 1.000s 19.953us 1 1 100.00
spi_host_csr_aliasing 2.000s 19.599us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 20.112us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.833us 1 1 100.00
spi_host_csr_rw 1.000s 19.953us 1 1 100.00
spi_host_csr_aliasing 2.000s 19.599us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 20.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 341.597us 1 1 100.00
spi_host_sec_cm 2.000s 287.501us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 341.597us 1 1 100.00