Simulation Results: sram_ctrl/main

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.60 %
  • code
  • 95.72 %
  • assert
  • 97.68 %
  • func
  • 93.40 %
  • block
  • 94.73 %
  • line
  • 95.25 %
  • branch
  • 91.57 %
  • toggle
  • 96.04 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 1355.696us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 16.095us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.701us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 195.199us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 58.849us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 1393.498us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 13.701us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 58.849us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 81.000s 2823.428us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 51.000s 10677.273us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 23.000s 16167.864us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 110.000s 3480.024us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 113.000s 6167.303us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 31.000s 14515.482us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 26.000s 7266.274us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 26.000s 24253.979us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 347.510us 1 1 100.00
sram_ctrl_partial_access_b2b 323.000s 284154.816us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 2756.989us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.000s 4776.782us 1 1 100.00
sram_ctrl_throughput_w_readback 8.000s 2685.881us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 958.345us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 696.752us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 116.000s 63756.913us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 12.252us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 25.443us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 25.443us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.095us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.701us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 58.849us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 13.787us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.095us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.701us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 58.849us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 13.787us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.000s 15379.031us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 579.183us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 384.799us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 579.183us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 384.799us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 958.345us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 958.345us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.701us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 26.000s 24253.979us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 26.000s 24253.979us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 26.000s 24253.979us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 26.000s 7266.274us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 1323.868us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.000s 15379.031us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 675.988us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1355.696us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1355.696us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 26.000s 24253.979us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 579.183us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 26.000s 7266.274us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 579.183us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 579.183us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 1355.696us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 579.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 10.000s 2197.777us 1 1 100.00