Simulation Results: sram_ctrl/ret

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.99 %
  • code
  • 83.30 %
  • assert
  • 98.08 %
  • func
  • 94.60 %
  • block
  • 93.66 %
  • line
  • 94.89 %
  • branch
  • 89.36 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 362.489us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 60.719us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.199us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 4.000s 787.195us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.846us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 55.394us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 15.199us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.846us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.000s 755.750us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.000s 57.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 9.000s 370.752us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 199.000s 5461.227us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 246.094us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 23.000s 3341.052us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1831.001us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 3.000s 376.375us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 46.063us 1 1 100.00
sram_ctrl_partial_access_b2b 151.000s 24030.890us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 514.985us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 59.583us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 112.879us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 607.861us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 285.369us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 35.000s 4774.318us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 16.911us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 258.527us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 258.527us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 60.719us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.199us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.846us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 24.326us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 60.719us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.199us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.846us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 24.326us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 798.610us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1233.528us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 269.941us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1233.528us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 269.941us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 607.861us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 607.861us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.199us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 3.000s 376.375us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 376.375us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 376.375us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1831.001us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 34.396us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 798.610us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 628.217us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 362.489us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 362.489us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 3.000s 376.375us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1233.528us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1831.001us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1233.528us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1233.528us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 362.489us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1233.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 21.000s 4998.171us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 19260602967473102850976380735656617385226543704555352335737946118863415907713 88
UVM_INFO @ 55393747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---