Simulation Results: sysrst_ctrl

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.05 %
  • code
  • 94.06 %
  • assert
  • 95.98 %
  • func
  • 65.11 %
  • line
  • 98.05 %
  • branch
  • 97.89 %
  • cond
  • 95.53 %
  • toggle
  • 100.00 %
  • FSM
  • 78.85 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.090s 2205.530us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.930s 2492.473us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.290s 2441.162us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.730s 2348.213us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 9.220s 4031.190us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.190s 2048.447us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 62.130s 76064.803us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.320s 2571.931us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.930s 2050.467us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.190s 2048.447us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.320s 2571.931us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 55.130s 126119.850us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 10.600s 51758.609us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 3.060s 3747.081us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.890s 3669.994us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.100s 2575.424us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.820s 2145.599us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.580s 3837.695us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 6.360s 2611.826us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.280s 8866.330us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 19.160s 40546.615us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 3.640s 7086.566us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.750s 2057.455us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.540s 2023.074us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.980s 2104.583us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.980s 2104.583us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 9.220s 4031.190us 1 1 100.00
sysrst_ctrl_csr_rw 2.190s 2048.447us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.320s 2571.931us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.990s 8719.458us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 9.220s 4031.190us 1 1 100.00
sysrst_ctrl_csr_rw 2.190s 2048.447us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.320s 2571.931us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.990s 8719.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 74.990s 42008.160us 1 1 100.00
sysrst_ctrl_tl_intg_err 79.920s 42404.066us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 79.920s 42404.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.170s 12577.903us 1 1 100.00