Simulation Results: uart

 
08/06/2026 15:30:24 DVSim: v1.49.9 sha: d730ff6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.19 %
  • code
  • 96.74 %
  • assert
  • 98.56 %
  • func
  • 51.28 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.78 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.350s 672.975us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.700s 73.132us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.560s 15.135us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.370s 257.179us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.870s 14.307us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.700s 19.608us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.560s 15.135us 1 1 100.00
uart_csr_aliasing 0.870s 14.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 27.630s 31530.398us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.350s 672.975us 1 1 100.00
uart_tx_rx 27.630s 31530.398us 1 1 100.00
parity_error 2 2 100.00
uart_intr 86.330s 86695.442us 1 1 100.00
uart_rx_parity_err 35.950s 32530.140us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 27.630s 31530.398us 1 1 100.00
uart_intr 86.330s 86695.442us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 30.180s 21265.072us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 29.210s 51328.665us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 47.720s 42212.230us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 86.330s 86695.442us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 86.330s 86695.442us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 86.330s 86695.442us 1 1 100.00
perf 1 1 100.00
uart_perf 89.260s 9268.538us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 17.590s 11420.984us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 17.590s 11420.984us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 5.760s 4576.522us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.230s 2937.490us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.780s 1220.547us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 31.700s 5255.157us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 238.790s 41995.108us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 65.590s 59287.578us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.660s 44.549us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.670s 16.348us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.690s 680.551us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.690s 680.551us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.700s 73.132us 1 1 100.00
uart_csr_rw 0.560s 15.135us 1 1 100.00
uart_csr_aliasing 0.870s 14.307us 1 1 100.00
uart_same_csr_outstanding 0.900s 108.436us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.700s 73.132us 1 1 100.00
uart_csr_rw 0.560s 15.135us 1 1 100.00
uart_csr_aliasing 0.870s 14.307us 1 1 100.00
uart_same_csr_outstanding 0.900s 108.436us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.810s 132.372us 1 1 100.00
uart_tl_intg_err 1.570s 902.792us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.570s 902.792us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 28.700s 14290.431us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 86803491746248777028906077184008784489001788009995077631414161825838005591530 76
UVM_ERROR @ 2770910759 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2770910759 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 2826744303 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 2826764921 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (229 [0xe5] vs 251 [0xfb]) reg name: uart_reg_block.rdata