Simulation Results: adc_ctrl

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.65 %
  • code
  • 92.23 %
  • assert
  • 91.90 %
  • func
  • 12.82 %
  • line
  • 97.97 %
  • branch
  • 96.23 %
  • cond
  • 86.10 %
  • toggle
  • 99.76 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 9.090s 5850.725us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.560s 1417.590us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.820s 489.313us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 53.870s 26624.007us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.950s 1199.817us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.960s 584.868us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.820s 489.313us 1 1 100.00
adc_ctrl_csr_aliasing 3.950s 1199.817us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.680s 495.766us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.980s 446.303us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 1.260s 472.994us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.700s 418.321us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.000s 488.110us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.830s 424.268us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.800s 416.902us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.110s 284.215us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 4.950s 2930.577us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 66.320s 45102.323us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 35.020s 63547.289us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 97.140s 58283.789us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.440s 519.294us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.710s 342.866us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.200s 408.089us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.200s 408.089us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.560s 1417.590us 1 1 100.00
adc_ctrl_csr_rw 0.820s 489.313us 1 1 100.00
adc_ctrl_csr_aliasing 3.950s 1199.817us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.010s 4793.145us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.560s 1417.590us 1 1 100.00
adc_ctrl_csr_rw 0.820s 489.313us 1 1 100.00
adc_ctrl_csr_aliasing 3.950s 1199.817us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.010s 4793.145us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 7.230s 4331.827us 1 1 100.00
adc_ctrl_tl_intg_err 2.260s 5350.248us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.260s 5350.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 4.030s 2407.279us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 100838236711510653518002475102463477391499744389210280149874910104665826248997 386
UVM_INFO @ 495765831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 57172106457652126191380726198232079749894842999954718983395177653057120991181 386
UVM_INFO @ 446303291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 105982278542995537576842328781703239926903726670839233498416301072199341996021 386
UVM_INFO @ 472994276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 15195111693872399601366042623253503758690224807556860879423594140290443251555 386
UVM_INFO @ 418320924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 46292767694008251565605787603229681054513322509092877464004248309670319190703 386
UVM_INFO @ 488110203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 113323425430106519555840096477705305271481720845043594301361165960253034264696 386
UVM_INFO @ 424267885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 91673000569900023367460253104640606100657506663500469215613479424918425573579 386
UVM_INFO @ 284214852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 2027296522452770035477614726735529319522708080519287260469990254836636898328 386
UVM_INFO @ 416901563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 36096222487041552274318652146182060971030850645337357386690668002794351234611 452
UVM_INFO @ 2407279365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 100982656568455464851503361966166274988284581040213376692813456760678482759231 554
UVM_INFO @ 58283788783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---