Simulation Results: aes/masked

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.30 %
  • code
  • 94.24 %
  • assert
  • 98.23 %
  • func
  • 75.44 %
  • block
  • 94.36 %
  • line
  • 96.03 %
  • branch
  • 87.37 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 298.538us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 504.874us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 64.267us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 105.970us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 125.935us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 92.475us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 205.297us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 105.970us 1 1 100.00
aes_csr_aliasing 2.000s 92.475us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 504.874us 1 1 100.00
aes_config_error 3.000s 161.212us 1 1 100.00
aes_stress 3.000s 63.395us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 504.874us 1 1 100.00
aes_config_error 3.000s 161.212us 1 1 100.00
aes_stress 3.000s 63.395us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 63.395us 1 1 100.00
aes_b2b 3.000s 107.219us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 63.395us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 504.874us 1 1 100.00
aes_config_error 3.000s 161.212us 1 1 100.00
aes_stress 3.000s 63.395us 1 1 100.00
aes_alert_reset 3.000s 177.137us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 106.666us 1 1 100.00
aes_config_error 3.000s 161.212us 1 1 100.00
aes_alert_reset 3.000s 177.137us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 195.331us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 1732.525us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 177.137us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 63.395us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 63.395us 1 1 100.00
aes_sideload 2.000s 217.517us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 120.600us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 18.000s 990.481us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 79.955us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 62.220us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 62.220us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 64.267us 1 1 100.00
aes_csr_rw 1.000s 105.970us 1 1 100.00
aes_csr_aliasing 2.000s 92.475us 1 1 100.00
aes_same_csr_outstanding 2.000s 94.772us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 64.267us 1 1 100.00
aes_csr_rw 1.000s 105.970us 1 1 100.00
aes_csr_aliasing 2.000s 92.475us 1 1 100.00
aes_same_csr_outstanding 2.000s 94.772us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 99.656us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 347.689us 1 1 100.00
aes_control_fi 3.000s 107.260us 1 1 100.00
aes_cipher_fi 3.000s 78.275us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 276.551us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 276.551us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 276.551us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 276.551us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 148.706us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 1023.544us 1 1 100.00
aes_tl_intg_err 2.000s 173.343us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 173.343us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 177.137us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 276.551us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 276.551us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 504.874us 1 1 100.00
aes_stress 3.000s 63.395us 1 1 100.00
aes_alert_reset 3.000s 177.137us 1 1 100.00
aes_core_fi 3.000s 76.898us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 161.212us 1 1 100.00
aes_stress 3.000s 63.395us 1 1 100.00
aes_core_fi 3.000s 76.898us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 276.551us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 52.191us 1 1 100.00
aes_stress 3.000s 63.395us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 63.395us 1 1 100.00
aes_sideload 2.000s 217.517us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 52.191us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 52.191us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 52.191us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 52.191us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 52.191us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 63.395us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 63.395us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 347.689us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 347.689us 1 1 100.00
aes_control_fi 3.000s 107.260us 1 1 100.00
aes_cipher_fi 3.000s 78.275us 1 1 100.00
aes_ctr_fi 2.000s 65.831us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 347.689us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 347.689us 1 1 100.00
aes_control_fi 3.000s 107.260us 1 1 100.00
aes_cipher_fi 3.000s 78.275us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 78.275us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 347.689us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 347.689us 1 1 100.00
aes_control_fi 3.000s 107.260us 1 1 100.00
aes_ctr_fi 2.000s 65.831us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 347.689us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 347.689us 1 1 100.00
aes_control_fi 3.000s 107.260us 1 1 100.00
aes_cipher_fi 3.000s 78.275us 1 1 100.00
aes_ctr_fi 2.000s 65.831us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 177.137us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 347.689us 1 1 100.00
aes_control_fi 3.000s 107.260us 1 1 100.00
aes_cipher_fi 3.000s 78.275us 1 1 100.00
aes_ctr_fi 2.000s 65.831us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 347.689us 1 1 100.00
aes_control_fi 3.000s 107.260us 1 1 100.00
aes_cipher_fi 3.000s 78.275us 1 1 100.00
aes_ctr_fi 2.000s 65.831us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 347.689us 1 1 100.00
aes_control_fi 3.000s 107.260us 1 1 100.00
aes_ctr_fi 2.000s 65.831us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 1 100.00
aes_fi 3.000s 347.689us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 347.689us 1 1 100.00
aes_control_fi 3.000s 107.260us 1 1 100.00
aes_cipher_fi 3.000s 78.275us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 23.655us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:1031) virtual_sequencer [aes_alert_reset_vseq] 1 test run
aes_stress_all_with_rand_reset 29134943636773959964816276841696153598781564908642007559000328176886281749168 148
Was able to clear FATAL ALERT without reset
---| Idle: 0
---| Stall: 0