Simulation Results: aes/unmasked

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.72 %
  • code
  • 90.10 %
  • assert
  • 97.73 %
  • func
  • 78.34 %
  • block
  • 90.28 %
  • line
  • 91.96 %
  • branch
  • 81.56 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 173.421us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 130.874us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 59.415us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 59.125us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 1158.040us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 498.739us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 98.093us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 59.125us 1 1 100.00
aes_csr_aliasing 3.000s 498.739us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 130.874us 1 1 100.00
aes_config_error 2.000s 109.946us 1 1 100.00
aes_stress 3.000s 68.299us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 130.874us 1 1 100.00
aes_config_error 2.000s 109.946us 1 1 100.00
aes_stress 3.000s 68.299us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 68.299us 1 1 100.00
aes_b2b 3.000s 101.044us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 68.299us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 130.874us 1 1 100.00
aes_config_error 2.000s 109.946us 1 1 100.00
aes_stress 3.000s 68.299us 1 1 100.00
aes_alert_reset 2.000s 90.021us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 64.986us 1 1 100.00
aes_config_error 2.000s 109.946us 1 1 100.00
aes_alert_reset 2.000s 90.021us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 81.238us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 552.555us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 90.021us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 68.299us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 68.299us 1 1 100.00
aes_sideload 2.000s 123.194us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 162.712us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 17.000s 2577.506us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 90.485us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 184.415us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 184.415us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 59.415us 1 1 100.00
aes_csr_rw 2.000s 59.125us 1 1 100.00
aes_csr_aliasing 3.000s 498.739us 1 1 100.00
aes_same_csr_outstanding 2.000s 192.976us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 59.415us 1 1 100.00
aes_csr_rw 2.000s 59.125us 1 1 100.00
aes_csr_aliasing 3.000s 498.739us 1 1 100.00
aes_same_csr_outstanding 2.000s 192.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 88.255us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 97.723us 1 1 100.00
aes_control_fi 2.000s 51.880us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 84.564us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 84.564us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 84.564us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 84.564us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 274.573us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 780.225us 1 1 100.00
aes_tl_intg_err 3.000s 184.709us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 184.709us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 90.021us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 84.564us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 84.564us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 130.874us 1 1 100.00
aes_stress 3.000s 68.299us 1 1 100.00
aes_alert_reset 2.000s 90.021us 1 1 100.00
aes_core_fi 2.000s 77.560us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 109.946us 1 1 100.00
aes_stress 3.000s 68.299us 1 1 100.00
aes_core_fi 2.000s 77.560us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 84.564us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 69.892us 1 1 100.00
aes_stress 3.000s 68.299us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 68.299us 1 1 100.00
aes_sideload 2.000s 123.194us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 69.892us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 69.892us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 69.892us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 69.892us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 69.892us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 68.299us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 68.299us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 2.000s 97.723us 1 1 100.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 97.723us 1 1 100.00
aes_control_fi 2.000s 51.880us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 62.650us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 2.000s 97.723us 1 1 100.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 97.723us 1 1 100.00
aes_control_fi 2.000s 51.880us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 2.000s 97.723us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 2.000s 97.723us 1 1 100.00
aes_control_fi 2.000s 51.880us 1 1 100.00
aes_ctr_fi 2.000s 62.650us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 2.000s 97.723us 1 1 100.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 97.723us 1 1 100.00
aes_control_fi 2.000s 51.880us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 62.650us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 90.021us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 97.723us 1 1 100.00
aes_control_fi 2.000s 51.880us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 62.650us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 97.723us 1 1 100.00
aes_control_fi 2.000s 51.880us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 62.650us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 2.000s 97.723us 1 1 100.00
aes_control_fi 2.000s 51.880us 1 1 100.00
aes_ctr_fi 2.000s 62.650us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 1 100.00
aes_fi 2.000s 97.723us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 97.723us 1 1 100.00
aes_control_fi 2.000s 51.880us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 8.000s 1504.487us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
aes_cipher_fi 38006271986219335231565160306155311525333396605545750845308532742652879422182 None
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 98222520126863233972384123204635851395752267915241381901637023156707236263213 418
UVM_INFO @ 1504486572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---