Simulation Results

Simulation Results: chip

09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
77.13 %

code
84.65 %

assert
97.37 %

func
49.37 %

line
94.11 %

branch
92.44 %

cond
88.34 %

toggle
91.23 %

FSM
57.14 %

Validation stages

V1		94.44%
V2		76.62%
V2S		100.00%
V3		65.38%
unmapped		63.64%

17/18 passed

94.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	170.570s	2457.962us	1	1	100.00
	chip_sw_example_rom	72.380s	2860.139us	1	1	100.00
	chip_sw_example_manufacturer	146.730s	2639.280us	1	1	100.00
	chip_sw_example_concurrency	192.160s	3297.002us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	138.340s	4940.286us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	459.260s	6797.523us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	3549.580s	55908.198us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	3279.740s	28965.487us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	chip_csr_mem_rw_with_rand_reset	51.380s	2424.421us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	3279.740s	28965.487us	1	1	100.00
	chip_csr_rw	459.260s	6797.523us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	4.530s	44.681us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	289.090s	4148.673us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	289.090s	4148.673us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	289.090s	4148.673us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	378.100s	4528.891us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	378.100s	4528.891us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	346.910s	4467.859us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	345.460s	4492.668us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	359.330s	4758.548us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	400.260s	4493.327us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1007.690s	7556.795us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	301.370s	4705.613us	1	1	100.00

213/278 passed

76.62 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	193.260s	6077.199us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	193.260s	6077.199us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				0	1	0.00
	chip_sw_sleep_pin_mio_dio_val	213.050s	4002.606us	0	1	0.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	340.360s	6116.462us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	179.620s	3860.727us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	586.630s	10475.062us	1	1	100.00
	chip_tap_straps_testunlock0	422.690s	7770.458us	1	1	100.00
	chip_tap_straps_rma	217.280s	4702.955us	1	1	100.00
	chip_tap_straps_prod	94.140s	2287.818us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	142.140s	2858.990us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	816.270s	9594.345us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	485.760s	5773.011us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	485.760s	5773.011us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	615.150s	6970.900us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1744.420s	16475.129us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	430.200s	4985.634us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	631.950s	6007.599us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3705.970s	19277.204us	1	1	100.00
	chip_sw_aes_enc_jitter_en	223.820s	3572.529us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	759.350s	6754.885us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	167.880s	3210.830us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1353.000s	11762.002us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	195.910s	3681.586us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	420.900s	5987.073us	1	1	100.00
	chip_sw_clkmgr_jitter	135.420s	3356.552us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	206.470s	3880.454us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	234.450s	3812.862us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	267.730s	5263.567us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	202.630s	3060.533us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	267.730s	5263.567us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	160.840s	3087.273us	1	1	100.00
	chip_sw_aes_smoketest	181.770s	3786.187us	1	1	100.00
	chip_sw_aon_timer_smoketest	192.990s	3069.159us	1	1	100.00
	chip_sw_clkmgr_smoketest	156.470s	2914.600us	1	1	100.00
	chip_sw_csrng_smoketest	174.640s	3130.118us	1	1	100.00
	chip_sw_entropy_src_smoketest	786.480s	6565.333us	1	1	100.00
	chip_sw_gpio_smoketest	221.400s	3029.642us	1	1	100.00
	chip_sw_hmac_smoketest	222.080s	3692.014us	1	1	100.00
	chip_sw_kmac_smoketest	227.430s	3506.093us	1	1	100.00
	chip_sw_otbn_smoketest	917.100s	7210.565us	1	1	100.00
	chip_sw_pwrmgr_smoketest	273.640s	5552.832us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	317.350s	6322.676us	1	1	100.00
	chip_sw_rv_plic_smoketest	145.800s	3278.907us	1	1	100.00
	chip_sw_rv_timer_smoketest	189.430s	2684.905us	1	1	100.00
	chip_sw_rstmgr_smoketest	137.570s	2742.138us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	162.940s	2985.743us	1	1	100.00
	chip_sw_uart_smoketest	160.170s	2943.926us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	162.510s	3172.514us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	324.370s	4127.848us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	8331.550s	62840.372us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	2968.680s	14678.509us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	104.190s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	213.680s	3534.729us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	179.990s	3654.930us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7236.190s	56487.721us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	8144.460s	57806.702us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	68.200s	2069.449us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	68.200s	2069.449us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	3279.740s	28965.487us	1	1	100.00
	chip_same_csr_outstanding	2297.620s	28272.285us	1	1	100.00
	chip_csr_hw_reset	138.340s	4940.286us	1	1	100.00
	chip_csr_rw	459.260s	6797.523us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	3279.740s	28965.487us	1	1	100.00
	chip_same_csr_outstanding	2297.620s	28272.285us	1	1	100.00
	chip_csr_hw_reset	138.340s	4940.286us	1	1	100.00
	chip_csr_rw	459.260s	6797.523us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	37.590s	629.376us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	6.230s	42.390us	1	1	100.00
	xbar_smoke_large_delays	54.040s	8215.813us	1	1	100.00
	xbar_smoke_slow_rsp	52.630s	5901.172us	1	1	100.00
	xbar_random_zero_delays	10.050s	115.214us	1	1	100.00
	xbar_random_large_delays	226.180s	37735.004us	1	1	100.00
	xbar_random_slow_rsp	116.610s	12205.358us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	33.230s	922.147us	1	1	100.00
	xbar_error_and_unmapped_addr	10.900s	324.507us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	33.720s	1497.888us	1	1	100.00
	xbar_error_and_unmapped_addr	10.900s	324.507us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	36.440s	520.976us	1	1	100.00
	xbar_access_same_device_slow_rsp	201.670s	23346.457us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	19.630s	328.336us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	182.840s	8600.118us	1	1	100.00
	xbar_stress_all_with_error	100.480s	2057.071us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	599.480s	8496.079us	1	1	100.00
	xbar_stress_all_with_reset_error	703.620s	22408.592us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	2968.680s	14678.509us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2660.960s	28262.988us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	2951.440s	18008.542us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	127.488s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	22.546s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	9.048s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	18.462s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	13.783s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	57.515s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	29.826s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.865s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.078s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	26.044s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	121.896s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	39.515s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	9.223s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	29.155s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	23.232s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18.630s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	26.940s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	21.490s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	24.000s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	23.080s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	23.430s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	21.350s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	24.090s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.820s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	22.120s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	19.200s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	20.080s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.770s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.330s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.820s	10.280us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	61.827s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	65.895s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	94.508s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	24.949s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	26.086s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	3188.370s	15504.614us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_no_meas	6150.010s	28946.915us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	6185.550s	28997.100us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3291.650s	16465.242us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3277.550s	34653.622us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3277.550s	34653.622us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	227.950s	2598.883us	1	1	100.00
	chip_sw_aes_enc_jitter_en	223.820s	3572.529us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	206.210s	3615.555us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	162.360s	3402.687us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1784.850s	13170.060us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	194.470s	3333.682us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	344.320s	5016.638us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	419.270s	5925.394us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	555.400s	4917.899us	1	1	100.00
	chip_plic_all_irqs_10	294.440s	3168.609us	1	1	100.00
	chip_plic_all_irqs_20	416.890s	4519.601us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	228.760s	3650.359us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1070.560s	15481.113us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	247.370s	3919.449us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	119.350s	3002.950us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.143s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1086.010s	8398.701us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	959.440s	7584.673us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	929.010s	8711.484us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9164.770s	255389.633us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	243.220s	3920.421us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	273.640s	5552.832us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	243.220s	3920.421us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	396.480s	7286.444us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	396.480s	7286.444us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	321.970s	6947.269us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	314.060s	5818.085us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	604.850s	6234.579us	1	1	100.00
	chip_sw_aes_idle	162.360s	3402.687us	1	1	100.00
	chip_sw_hmac_enc_idle	182.440s	3463.344us	1	1	100.00
	chip_sw_kmac_idle	202.720s	3787.529us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	308.270s	4487.341us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	329.170s	5578.985us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	402.350s	6164.225us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	236.910s	3931.645us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	1049.080s	12330.961us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	404.570s	4311.199us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	423.260s	5531.077us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	407.700s	4174.685us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	378.060s	4707.163us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	366.440s	3970.122us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	437.140s	5403.222us	1	1	100.00
	chip_sw_ast_clk_outputs	615.150s	6970.900us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	616.720s	11325.406us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	407.700s	4174.685us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	378.060s	4707.163us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	430.200s	4985.634us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	631.950s	6007.599us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3705.970s	19277.204us	1	1	100.00
	chip_sw_aes_enc_jitter_en	223.820s	3572.529us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	759.350s	6754.885us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	167.880s	3210.830us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1353.000s	11762.002us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	195.910s	3681.586us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	420.900s	5987.073us	1	1	100.00
	chip_sw_clkmgr_jitter	135.420s	3356.552us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	139.510s	2369.945us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	369.160s	4591.237us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	705.300s	7602.417us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3993.880s	25275.636us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	147.140s	2728.893us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	180.360s	3441.128us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	867.660s	9275.666us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	189.710s	3430.651us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	387.610s	5240.708us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1341.740s	25698.860us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	1504.730s	13367.495us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	615.150s	6970.900us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	365.210s	4791.641us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	298.620s	3482.375us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	419.270s	5925.394us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1086.010s	8398.701us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2089.000s	24560.606us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	199.950s	3160.691us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	533.860s	6359.469us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	159.790s	2721.880us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	3502.960s	20165.102us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	140.630s	2502.640us	1	1	100.00
	chip_sw_edn_entropy_reqs	863.100s	7259.565us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	140.630s	2502.640us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2089.000s	24560.606us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	123.830s	2584.899us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1231.870s	20634.728us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	551.640s	6367.089us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	631.950s	6007.599us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	347.620s	4261.147us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	430.200s	4985.634us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3839.860s	42775.587us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1231.870s	20634.728us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	204.160s	3444.770us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	951.300s	8479.042us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	200.200s	3157.429us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3839.860s	42775.587us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	200.200s	3157.429us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	200.200s	3157.429us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	200.200s	3157.429us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	200.200s	3157.429us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	419.270s	5925.394us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	306.120s	13443.225us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	560.310s	5676.975us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	385.570s	4801.336us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	385.570s	4801.336us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	217.460s	3290.672us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	167.880s	3210.830us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	182.440s	3463.344us	1	1	100.00
chip_sw_hmac_all_configurations				0	1	0.00
	chip_sw_hmac_oneshot	1766.340s	12018.705us	0	1	0.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1622.100s	12018.360us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	510.910s	5112.720us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	381.630s	5053.231us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	413.030s	5619.697us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	273.020s	4163.751us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	951.300s	8479.042us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1353.000s	11762.002us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1588.520s	10967.593us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1784.850s	13170.060us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4613.820s	20026.711us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	166.840s	3061.720us	1	1	100.00
	chip_sw_kmac_mode_kmac	258.470s	3751.339us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	195.910s	3681.586us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	951.300s	8479.042us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	234.520s	5115.911us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	164.050s	3168.284us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1084.320s	8584.453us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	202.720s	3787.529us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	344.320s	5016.638us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	586.630s	10475.062us	1	1	100.00
	chip_tap_straps_rma	217.280s	4702.955us	1	1	100.00
	chip_tap_straps_prod	94.140s	2287.818us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	139.310s	2931.628us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	234.520s	5115.911us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	234.520s	5115.911us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	234.520s	5115.911us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1841.620s	13460.052us	1	1	100.00
chip_sw_lc_ctrl_broadcast				20	22	90.91
	chip_sw_flash_ctrl_lc_rw_en	200.200s	3157.429us	0	1	0.00
	chip_sw_flash_rma_unlocked	3839.860s	42775.587us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	224.400s	3487.526us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	614.120s	8452.356us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	511.600s	6429.347us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	543.090s	6505.411us	0	1	0.00
	chip_sw_lc_ctrl_transition	234.520s	5115.911us	1	1	100.00
	chip_sw_keymgr_key_derivation	951.300s	8479.042us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	398.920s	9355.952us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	457.310s	6926.908us	1	1	100.00
	chip_prim_tl_access	306.120s	13443.225us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	616.720s	11325.406us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	404.570s	4311.199us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	423.260s	5531.077us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	407.700s	4174.685us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	378.060s	4707.163us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	366.440s	3970.122us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	437.140s	5403.222us	1	1	100.00
	chip_tap_straps_dev	586.630s	10475.062us	1	1	100.00
	chip_tap_straps_rma	217.280s	4702.955us	1	1	100.00
	chip_tap_straps_prod	94.140s	2287.818us	1	1	100.00
	chip_rv_dm_lc_disabled	418.800s	17103.429us	1	1	100.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	171.710s	3119.251us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	99.590s	3677.136us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	95.570s	3051.827us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	141.040s	3593.083us	1	1	100.00
chip_lc_test_locked				2	2	100.00
	chip_sw_lc_walkthrough_testunlocks	1482.510s	29572.469us	1	1	100.00
	chip_rv_dm_lc_disabled	418.800s	17103.429us	1	1	100.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	660.170s	8806.538us	0	1	0.00
	chip_sw_lc_walkthrough_prod	685.390s	9592.901us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	769.600s	11176.111us	1	1	100.00
	chip_sw_lc_walkthrough_rma	305.510s	5278.008us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1482.510s	29572.469us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	63.340s	2388.853us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	78.520s	2924.098us	1	1	100.00
	rom_volatile_raw_unlock	144.613s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3829.520s	17518.898us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3705.970s	19277.204us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	604.850s	6234.579us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	604.850s	6234.579us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	604.850s	6234.579us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	359.850s	4011.905us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	234.520s	5115.911us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1231.870s	20634.728us	1	1	100.00
	chip_sw_otbn_mem_scramble	359.850s	4011.905us	1	1	100.00
	chip_sw_keymgr_key_derivation	951.300s	8479.042us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	373.730s	4356.308us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	183.630s	2991.748us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1231.870s	20634.728us	1	1	100.00
	chip_sw_otbn_mem_scramble	359.850s	4011.905us	1	1	100.00
	chip_sw_keymgr_key_derivation	951.300s	8479.042us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	373.730s	4356.308us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	183.630s	2991.748us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	234.520s	5115.911us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	409.220s	4941.247us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	139.310s	2931.628us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	224.400s	3487.526us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	614.120s	8452.356us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	511.600s	6429.347us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	543.090s	6505.411us	0	1	0.00
	chip_sw_lc_ctrl_transition	234.520s	5115.911us	1	1	100.00
	chip_prim_tl_access	306.120s	13443.225us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	306.120s	13443.225us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	940.890s	7728.192us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	155.560s	5988.742us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	906.420s	22731.970us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	303.200s	7658.420us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	356.360s	7296.460us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	476.960s	6714.347us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	919.610s	21056.431us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				0	2	0.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	468.230s	10977.860us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	396.480s	7286.444us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	941.860s	11113.570us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	327.400s	4847.015us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	155.560s	5988.742us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	252.120s	4165.746us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1876.590s	35780.523us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	380.370s	7135.279us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	169.210s	3074.318us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	699.980s	14672.710us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	660.700s	7295.718us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	876.960s	9433.537us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	2026.260s	26656.122us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	170.190s	3006.339us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	419.270s	5925.394us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	398.920s	9355.952us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	398.920s	9355.952us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	876.960s	9433.537us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	699.980s	14672.710us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	327.400s	4847.015us	1	1	100.00
	chip_sw_pwrmgr_smoketest	273.640s	5552.832us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	271.840s	4367.294us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	408.300s	6594.915us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	257.530s	3904.593us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1070.560s	15481.113us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	146.360s	3011.069us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	419.270s	5925.394us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	959.440s	7584.673us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	499.210s	4826.648us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	536.360s	4829.270us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	226.720s	3793.290us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	183.630s	2991.748us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	408.300s	6594.915us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	408.300s	6594.915us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	697.350s	10895.107us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	967.750s	13179.566us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	271.840s	4367.294us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	209.810s	3778.139us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	309.540s	6448.733us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	217.280s	4702.955us	1	1	100.00
chip_rv_dm_lc_disabled				1	1	100.00
	chip_rv_dm_lc_disabled	418.800s	17103.429us	1	1	100.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	555.400s	4917.899us	1	1	100.00
	chip_plic_all_irqs_10	294.440s	3168.609us	1	1	100.00
	chip_plic_all_irqs_20	416.890s	4519.601us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	135.270s	2803.471us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	177.420s	3585.969us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	2968.680s	14678.509us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	290.650s	4524.739us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	221.900s	3480.859us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	218.780s	3575.548us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	165.930s	2709.092us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	373.730s	4356.308us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	420.900s	5987.073us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	352.130s	8157.700us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	578.360s	8324.137us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	457.310s	6926.908us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	419.270s	5925.394us	1	1	100.00
	chip_sw_data_integrity_escalation	485.760s	5773.011us	1	1	100.00
chip_sw_sysrst_ctrl_reset				1	2	50.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	660.700s	7295.718us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	871.540s	23705.623us	0	1	0.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	196.900s	2535.409us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	243.890s	4088.642us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	377.320s	4545.097us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				0	1	0.00
	chip_sw_sysrst_ctrl_reset	871.540s	23705.623us	0	1	0.00
chip_sw_sysrst_ctrl_sleep_reset				0	1	0.00
	chip_sw_sysrst_ctrl_reset	871.540s	23705.623us	0	1	0.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2648.340s	20427.867us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2648.340s	20427.867us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	353.510s	5768.820us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3277.550s	34653.622us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	167.830s	2529.102us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	183.810s	2902.755us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	251.910s	4077.072us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	365.690s	3552.632us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	1036.350s	8458.149us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5756.380s	31888.831us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1958.560s	12176.949us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	196.410s	3105.671us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	241.930s	3777.358us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	172.030s	3187.100us	1	1	100.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	10515.860s	71856.671us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1144.050s	6884.856us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	211.640s	5086.541us	0	1	0.00
	rom_e2e_jtag_debug_dev	158.810s	3741.040us	0	1	0.00
	rom_e2e_jtag_debug_rma	526.900s	6683.584us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	58.490s	2052.510us	0	1	0.00
	rom_e2e_jtag_inject_dev	57.950s	2284.699us	0	1	0.00
	rom_e2e_jtag_inject_rma	62.240s	2248.788us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	171.099s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	267.910s	3910.758us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	342.620s	2803.560us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	856.660s	5129.326us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1428.980s	10172.199us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	250.240s	2688.205us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	556.250s	5038.833us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	145.230s	3464.556us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	161.030s	3191.693us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	258.510s	5613.798us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	302.290s	5959.961us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	876.960s	9433.537us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	211.640s	5086.541us	0	1	0.00
	rom_e2e_jtag_debug_dev	158.810s	3741.040us	0	1	0.00
	rom_e2e_jtag_debug_rma	526.900s	6683.584us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	345.860s	5163.420us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	419.270s	5925.394us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5897.220s	38485.169us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5897.220s	38485.169us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	199.170s	3267.384us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	378.100s	4528.891us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	2818.080s	18399.500us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	208.890s	2838.590us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	19.080s	10.240us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	4.870s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	158.240s	2809.730us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	185.270s	2901.932us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	252.810s	3805.466us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	9.498s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	187.500s	2600.866us	1	1	100.00
	ate_bootstrap_flash_erase	654.970s	10010.380us	0	1	0.00
	ate_bootstrap_one_frame	6953.690s	45483.500us	1	1	100.00
	ate_bootstrap_disjoint	9850.280s	85015.645us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	14427701572919383515334513353572805394516081857395201081426001154933304006475	None	---- STDERR ---- Another command (pid=2085490) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	88224028543510572482910042460008160424089891591204004058735728312144393719372	None	Another command (pid=567713) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=417902) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=570131) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	106510368976213660956997734334785134918839372181441464396145585061245692360584	None	Another command (pid=605215) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=641884) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=648471) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	92628127656505465237924504221667486351865781822776954343490235811099969701731	None	---- STDERR ---- Another command (pid=613192) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=578016) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	108182584620840045746582041876510052970473375465382733852938574632760302116652	None	Another command (pid=651298) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=662935) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=666957) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	86968488723971103582552778676970528585793151987488063173719049433277690180205	None	Another command (pid=634097) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=641884) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=648471) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	64785743922066265470138869387938383770546187804606506122699656627425969057840	None	Another command (pid=381419) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=398181) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=430793) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	56833981847301555705045971523532255173148177647367261431021972940240497741626	None	Another command (pid=582690) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=627960) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=585380) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	53499802930244012691204982725111475921014004224721431700500621736018059108991	None	---- STDERR ---- Another command (pid=588624) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=577497) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	4105767476794177734658574545950243888146010435144310286045845514615794848841	None	Another command (pid=627960) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=585380) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=599832) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	56812780688943814772111860177492467798655642290155388434209058350432767499860	None	Another command (pid=662935) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=626292) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=666957) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13181111828608640350869511921184147207503196969902790529560051066418683812716	None	Another command (pid=429435) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=465439) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=466939) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	64333864436956681788650275438781748294020715808095096856429134220360859453889	None	Another command (pid=577497) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=630013) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=639158) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	91529519827396668656594539409301270814235552842542009460933260893062921234648	None	---- STDERR ---- Another command (pid=574371) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=580049) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17285668256888780520349938204828651956232436656534267932638149330436896585924	None	Another command (pid=589747) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=611436) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=609484) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	59357844190375635953062973719250009358934379611776955205951444726190925474161	None	Another command (pid=611436) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=609484) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=613978) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	22996180802027109700626466699468325280271138086526868432905400203029740580715	None	Another command (pid=398181) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=430793) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=429435) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	15515257054892607644330820904243335445033279813372187455591129613551661175543	None	Another command (pid=467377) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=468394) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=458194) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	67635340176928736433800158800819774608062305888180324419996985989241413613123	None	Another command (pid=589747) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=611436) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=609484) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	2587829481031283590748281977389569047612513592000227188243722469289541499508	None	Another command (pid=467377) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=468394) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=471911) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	21195871192856900270418506698770286179773101150784883069823040626035107531270	None	Another command (pid=607365) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=608362) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=595893) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	90060353028772423335306292784931434745455280247338218227943631923320017804405	None	Another command (pid=627960) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=585380) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=646400) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	94013218222976767594418947802825200374604874934115607887245917976223583543258	None	Another command (pid=399808) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=384350) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=466939) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	103260833193464626639393960338999576737492699023428479531667891966326895923077	None	Another command (pid=666957) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=682169) is running. Waiting for it to complete on the server (server_pid=296371)... Another command (pid=575651) is running. Waiting for it to complete on the server (server_pid=296371)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				7 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	98419755923660576682266948839909868539161713456018195538452177655929233619041	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	5582972200806175275177486405069606312014420499575910471460993140801250189779	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	97059063047335223563024777721417990443196354169519596684891584757107716045137	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	84071941468041242707772717348929700367077760828993984561167963334534190731545	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	14811146969461600260739264990502637350509203294971421553223370441911342358231	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	56093520669961869075449173929772751274026280148793571277907100694547696573985	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	71917355218433890894950711464517773963863923639878874333877325834619890816520	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	51457181503184044134878817739103970755476924573722192490641667526567883886151	368	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	61268874634779454818526626040761516480861942306013965984228432854441321852928	365	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	64908080757556256206937552496714455010133985993899275491053756445291815139843	365	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	65266029686731089568521974363229867163869467466912711530718833907444368857481	328	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	52541225303650560397692385044993554197710497374258267217298467229737555029034	327	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	59700452592704172927181412176199060873269945994788955017498381298904977662712	328	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				4 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	65719383363642126986675340997340961370621655834904005658410294754093031333394	344	UVM_ERROR @ 14672.710000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 14672.710000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	30669208660124560235894262058384831251631633941317675874650491779292960001433	327	UVM_ERROR @ 10977.860000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 10977.860000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sysrst_ctrl_reset	89042559835556312706622415806526055700048663460685730284212352657912167879913	334	UVM_ERROR @ 23705.622500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 23705.622500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	44563624764105364059571791937052169368372071450276139905090405594482078395549	319	UVM_ERROR @ 7286.444000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7286.444000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	13817882522327450775239590444953217447508581357684252067152758872171920099523	369	UVM_INFO @ 8806.537842 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	49368758692887808522116541358003401591265656936088217978356263744237294238781	369	UVM_INFO @ 9592.900807 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	30397390098689846824027104173323136606018922254558237377177449150957077884367	341	UVM_INFO @ 5278.007808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				3 test runs
	chip_sw_hmac_oneshot	43593683689977914913591594615924457558370915863326942807238266069627044841335	310	UVM_INFO @ 12018.704637 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_hmac_multistream	6230824448483579709163241291624128079431047213923325032609647955671237515861	310	UVM_INFO @ 12018.360331 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	49784027253687730956280108840024826527653438563685232223877483473253431992569	336	UVM_INFO @ 20026.711240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	71612719063014919148044867837260588757787016788599476305923294768147620840114	326	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	7174116453838964494049657440631355186455886391643944462571528691355635278271	325	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	103822562440338773058288253803939399412393603295988340010796706065957155859748	328	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				2 test runs
	chip_sw_otp_ctrl_escalation	110380885650100811259201008026710406424203290801669929116019340774710143627612	316	UVM_ERROR @ 3191.692700 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3191.692700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	89355902486796672457668040550881881986781910718209966996773454548354088445848	312	UVM_ERROR @ 3160.691072 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3160.691072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				2 test runs
	chip_tl_errors	78512087986310473390069372086761116832234943905933317915536229568038933516439	217	TL item was: req: (cip_tl_seq_item@42808) { a_addr: 'h10410 a_data: 'hee544a82 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h1b143 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2069.449440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_csr_mem_rw_with_rand_reset	62300096780679073892820373814460725576169622828653722401723843836554272051524	224	TL item was: req: (cip_tl_seq_item@32678) { a_addr: 'h107e8 a_data: 'h4b84bb45 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h18db3 d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2424.421380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	28358878643437743400693325392773970485984099300977703240213519260117994440174	363	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	27630498548614960874407406705928383640593867887213232505901121605574792271757	325	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	68580116070325943212687876415351332706131689946497675003951539216391239516295	365	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	101161724081640364849816582967957181604942733371771607998581476602637019711738	328	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	103844827613594192343199395860977564169258411408978031091815440133933992919609	301	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [] vs xz [z]) for MIO[*]				1 test run
	chip_sw_sleep_pin_mio_dio_val	43598042371645562079539797322447069247490696420003438172309773242842619150143	451	UVM_INFO @ 4002.605500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	48745832251889843202386066477519508085866975633509156578285480816716902186509	327	UVM_INFO @ 3480.858744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	3869295472800393521120690097204502673653159867478212992722571194758334535558	309	UVM_INFO @ 3157.429000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	61157616843560416909426007535554222257492042068222972841302953717036664020977	342	UVM_INFO @ 6505.411435 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	73420479202375157832643487841958446510074776434821604519896888070966850566180	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	22273732673027817969724019227792032296389154246716680368077334947065710756176	322	UVM_ERROR @ 5988.741522 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 5988.741522 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	86950918621868149981810018705294619672732415615885343319601499936737929973154	313	UVM_ERROR @ 3074.318224 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3074.318224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	19973106419954477391075759171760872893439763559062184149633896108249610945559	332	UVM_INFO @ 34653.622156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	26361059382921048586924749186808294325581818938186665712414644466617621099903	307	UVM_INFO @ 3333.682487 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	84223618085161719470398639186622412312614696143955236486743224487965825561969	308	UVM_INFO @ 3002.950388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	11889571184114362407420124276468446926450063965400896243181086888435387336108	None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	29332883552686291683025662692935950419127882254602364666730277092316102829330	343	UVM_INFO @ 3910.757973 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_idle_load	83037092658671822093296479846050426995317122539297927884056465050788656692926	312	UVM_INFO @ 3534.729500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_sleep_load	85811330724655243825475843930478628526826145764326251367516359641158137969860	318	UVM_INFO @ 3654.930000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	56656096652863846413143062046544709875106314407544735402546811176263293075713	327	UVM_INFO @ 16475.129317 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	33766587772319322002896577150487862002972167187908944481194421062865358555283	272	UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	64530412498986662552936851563017959180252398722283155571668679841543383710282	325	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	84922257557748393543074082402405528120265187056799942871747538574800223956517	326	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_meas	82049446310357202149835018203607304445679140397153181323026073029451355423935	319	UVM_INFO @ 15504.614170 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	89525978225273099241190063329411379180849427769306931975612081225991037062153	327	UVM_ERROR @ 4127.848029 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4127.848029 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---