Simulation Results: clkmgr

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.59 %
  • code
  • 97.83 %
  • assert
  • 94.35 %
  • func
  • 85.59 %
  • line
  • 98.90 %
  • branch
  • 98.64 %
  • cond
  • 92.41 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.630s 214.039us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.770s 46.755us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.790s 18.475us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.650s 450.956us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.470s 155.943us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.960s 38.498us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.790s 18.475us 1 1 100.00
clkmgr_csr_aliasing 1.470s 155.943us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.730s 40.012us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.020s 83.689us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.110s 144.110us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.710s 46.924us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.630s 214.039us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 2.380s 444.293us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 10.560s 2296.617us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 2.380s 444.293us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 0.890s 52.355us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.760s 49.352us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.800s 145.374us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.800s 145.374us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.770s 46.755us 1 1 100.00
clkmgr_csr_rw 0.790s 18.475us 1 1 100.00
clkmgr_csr_aliasing 1.470s 155.943us 1 1 100.00
clkmgr_same_csr_outstanding 1.360s 65.645us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.770s 46.755us 1 1 100.00
clkmgr_csr_rw 0.790s 18.475us 1 1 100.00
clkmgr_csr_aliasing 1.470s 155.943us 1 1 100.00
clkmgr_same_csr_outstanding 1.360s 65.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.990s 11.818us 0 1 0.00
clkmgr_tl_intg_err 2.160s 146.964us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 433.060s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 433.060s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 433.060s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 433.060s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.920s 80.678us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.160s 146.964us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 2.380s 444.293us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 10.560s 2296.617us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 433.060s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.970s 65.644us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.890s 30.199us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.130s 84.905us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.790s 52.295us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.020s 113.522us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.790s 18.475us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.990s 11.818us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 18.475us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 18.475us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.990s 11.818us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.920s 932.502us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 62.440s 13550.347us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 67288769999246344409599881880003160205591648189070166444072488506848946052082 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 26913301906363093136825547271782118872667385494122042243900207815645741831003 85
UVM_INFO @ 11818350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---