Simulation Results: csrng

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.01 %
  • code
  • 92.18 %
  • assert
  • 93.89 %
  • func
  • 77.96 %
  • block
  • 96.89 %
  • line
  • 97.66 %
  • branch
  • 92.26 %
  • toggle
  • 93.10 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 42.847us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 37.216us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 18.681us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 15.000s 726.111us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 272.148us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 114.073us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 18.681us 1 1 100.00
csrng_csr_aliasing 5.000s 272.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
alerts 1 1 100.00
csrng_alert 13.000s 748.247us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 130.830us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 130.830us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 443.000s 20197.499us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 18.093us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 8.000s 45.853us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 467.151us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 467.151us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 37.216us 1 1 100.00
csrng_csr_rw 2.000s 18.681us 1 1 100.00
csrng_csr_aliasing 5.000s 272.148us 1 1 100.00
csrng_same_csr_outstanding 3.000s 27.317us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 37.216us 1 1 100.00
csrng_csr_rw 2.000s 18.681us 1 1 100.00
csrng_csr_aliasing 5.000s 272.148us 1 1 100.00
csrng_same_csr_outstanding 3.000s 27.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 7.000s 843.528us 1 1 100.00
csrng_tl_intg_err 3.000s 63.546us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 25.156us 1 1 100.00
csrng_csr_rw 2.000s 18.681us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 13.000s 748.247us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 443.000s 20197.499us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
csrng_sec_cm 7.000s 843.528us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
csrng_sec_cm 7.000s 843.528us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
csrng_sec_cm 7.000s 843.528us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
csrng_sec_cm 7.000s 843.528us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
csrng_sec_cm 7.000s 843.528us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 13.000s 748.247us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 443.000s 20197.499us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 13.000s 748.247us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 63.546us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
csrng_sec_cm 7.000s 843.528us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
csrng_sec_cm 7.000s 843.528us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 14.000s 1367.993us 1 1 100.00
csrng_err 1.000s 25.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 1 test run
csrng_cmds 106269400537816820267716573649387060322891195869796382656408478905168332011594 103
UVM_INFO @ 130830277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 78215168083333712454256971220898058376966634530199612878191166132673451754152 None