Simulation Results: edn/edn0

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.69 %
  • code
  • 75.34 %
  • assert
  • 96.53 %
  • func
  • 76.19 %
  • line
  • 95.54 %
  • branch
  • 85.91 %
  • cond
  • 79.86 %
  • toggle
  • 72.90 %
  • FSM
  • 42.47 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 36.689us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.870s 15.020us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 28.270us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.870s 256.917us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.950s 16.249us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.930s 154.527us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 28.270us 1 1 100.00
edn_csr_aliasing 0.950s 16.249us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.960s 54.456us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.960s 54.456us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.960s 54.456us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.140s 37.615us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.170s 53.263us 1 1 100.00
errs 1 1 100.00
edn_err 0.980s 21.332us 1 1 100.00
disable 1 2 50.00
edn_disable 0.840s 63.657us 1 1 100.00
edn_disable_auto_req_mode 1.290s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.050s 196.420us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.050s 20.701us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.750s 45.286us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.630s 259.195us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.630s 259.195us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.870s 15.020us 1 1 100.00
edn_csr_rw 0.810s 28.270us 1 1 100.00
edn_csr_aliasing 0.950s 16.249us 1 1 100.00
edn_same_csr_outstanding 1.160s 111.100us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.870s 15.020us 1 1 100.00
edn_csr_rw 0.810s 28.270us 1 1 100.00
edn_csr_aliasing 0.950s 16.249us 1 1 100.00
edn_same_csr_outstanding 1.160s 111.100us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.900s 1215.116us 1 1 100.00
edn_tl_intg_err 1.800s 325.265us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.930s 22.413us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.170s 53.263us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.900s 1215.116us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.900s 1215.116us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.900s 1215.116us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.900s 1215.116us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.170s 53.263us 1 1 100.00
edn_sec_cm 3.900s 1215.116us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.170s 53.263us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.800s 325.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 36.280s 2256.517us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 62708732738323505938693975180256695102605323681896279985523114161785451260756 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---