Simulation Results: edn/edn1

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.18 %
  • code
  • 82.47 %
  • assert
  • 98.18 %
  • func
  • 80.88 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 89.31 %
  • toggle
  • 87.03 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.770s 55.452us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 48.109us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 14.384us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.650s 605.846us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.240s 136.957us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.020s 26.031us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 14.384us 1 1 100.00
edn_csr_aliasing 1.240s 136.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.240s 53.041us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.240s 53.041us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.240s 53.041us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 22.947us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.950s 44.673us 1 1 100.00
errs 1 1 100.00
edn_err 1.020s 183.003us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 18.517us 1 1 100.00
edn_disable_auto_req_mode 0.990s 51.785us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.440s 638.884us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.700s 45.473us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.060s 27.169us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.580s 439.399us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.580s 439.399us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 48.109us 1 1 100.00
edn_csr_rw 0.760s 14.384us 1 1 100.00
edn_csr_aliasing 1.240s 136.957us 1 1 100.00
edn_same_csr_outstanding 1.030s 60.332us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 48.109us 1 1 100.00
edn_csr_rw 0.760s 14.384us 1 1 100.00
edn_csr_aliasing 1.240s 136.957us 1 1 100.00
edn_same_csr_outstanding 1.030s 60.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.240s 1140.940us 1 1 100.00
edn_tl_intg_err 2.250s 145.926us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 19.791us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.950s 44.673us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.240s 1140.940us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.240s 1140.940us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.240s 1140.940us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.240s 1140.940us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.950s 44.673us 1 1 100.00
edn_sec_cm 4.240s 1140.940us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.950s 44.673us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.250s 145.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 50.430s 7872.675us 1 1 100.00