Simulation Results: entropy_src/rng_4bits

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.11 %
  • code
  • 87.44 %
  • assert
  • 84.56 %
  • func
  • 50.34 %
  • block
  • 94.23 %
  • line
  • 96.91 %
  • branch
  • 86.25 %
  • toggle
  • 75.99 %
  • FSM
  • 90.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 105.440us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 28.131us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 25.902us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 6.000s 906.300us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 191.114us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 59.202us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 25.902us 1 1 100.00
entropy_src_csr_aliasing 4.000s 191.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 105.440us 1 1 100.00
entropy_src_rng 219.000s 13047.376us 1 1 100.00
entropy_src_fw_ov 243.000s 14039.996us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 243.000s 14039.996us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 219.000s 13047.376us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 44.000s 14612.089us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 219.000s 13047.376us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 219.000s 13047.376us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 219.000s 13047.376us 1 1 100.00
entropy_src_intr 8.000s 869.954us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 219.000s 13047.376us 1 1 100.00
entropy_src_functional_alerts 5.000s 852.305us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 59.000s 14110.299us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 42.629us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 32.865us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 17.991us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 132.502us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 54.825us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 54.825us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 28.131us 1 1 100.00
entropy_src_csr_rw 2.000s 25.902us 1 1 100.00
entropy_src_csr_aliasing 4.000s 191.114us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 147.518us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 28.131us 1 1 100.00
entropy_src_csr_rw 2.000s 25.902us 1 1 100.00
entropy_src_csr_aliasing 4.000s 191.114us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 147.518us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 177.057us 1 1 100.00
entropy_src_tl_intg_err 3.000s 268.910us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 219.000s 13047.376us 1 1 100.00
entropy_src_cfg_regwen 1.000s 26.148us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 219.000s 13047.376us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 219.000s 13047.376us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 219.000s 13047.376us 1 1 100.00
entropy_src_fw_ov 243.000s 14039.996us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 42.629us 1 1 100.00
entropy_src_sec_cm 2.000s 177.057us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 42.629us 1 1 100.00
entropy_src_sec_cm 2.000s 177.057us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 219.000s 13047.376us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 42.629us 1 1 100.00
entropy_src_sec_cm 2.000s 177.057us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 42.629us 1 1 100.00
entropy_src_sec_cm 2.000s 177.057us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 42.629us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 852.305us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 268.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 63.000s 13303.586us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 12.000s 2823.381us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 42010517801541223484990189394457686904787048559271305520290079793409215508100 580
UVM_INFO @ 2823380561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---