Simulation Results: flash_ctrl

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.67 %
  • code
  • 94.02 %
  • assert
  • 96.93 %
  • func
  • 96.07 %
  • line
  • 95.90 %
  • branch
  • 97.01 %
  • cond
  • 93.48 %
  • toggle
  • 97.33 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 46.570s 66.287us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.940s 32.989us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 16.230s 46.042us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.810s 112.862us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 41.850s 1270.081us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 43.550s 1508.287us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.020s 27.520us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.810s 112.862us 1 1 100.00
flash_ctrl_csr_aliasing 43.550s 1508.287us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 8.470s 17.503us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.880s 58.656us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 12.440s 199.963us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 39.920s 78.036us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1123.430s 171374.581us 1 1 100.00
flash_ctrl_hw_rma_reset 526.320s 40125.013us 1 1 100.00
flash_ctrl_lcmgr_intg 7.150s 42.359us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1768.240s 1746829.260us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 224.660s 2133.025us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 122.800s 5393.968us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2986.960s 50872.797us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 74.110s 2821.037us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 14.730s 44.737us 1 1 100.00
flash_ctrl_rw_evict_all_en 16.760s 43.572us 1 1 100.00
flash_ctrl_re_evict 18.100s 120.479us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 46.670s 66.403us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 46.670s 66.403us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 166.040s 12569.416us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 18.980s 412.498us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 419.620s 1298.653us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 650.490s 12635.559us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 360.220s 1019.544us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1122.140s 11755.361us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.890s 210.930us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 138.310s 1501.501us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.480s 73.396us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.620s 70.073us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 641.420s 400.902us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 120.290s 14620.425us 1 1 100.00
flash_ctrl_otp_reset 59.010s 137.975us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1123.430s 171374.581us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 69.740s 1606.974us 1 1 100.00
flash_ctrl_intr_wr 56.250s 11369.292us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 221.340s 13326.400us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 139.240s 46133.554us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 52.020s 3575.270us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 41.170s 4218.019us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.660s 25.184us 1 1 100.00
flash_ctrl_ro_derr 82.310s 9865.984us 1 1 100.00
flash_ctrl_rw_derr 159.310s 5262.887us 1 1 100.00
flash_ctrl_derr_detect 119.870s 2860.107us 1 1 100.00
flash_ctrl_integrity 435.570s 9249.433us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.310s 77.745us 1 1 100.00
flash_ctrl_ro_serr 98.800s 1099.331us 1 1 100.00
flash_ctrl_rw_serr 170.760s 7928.829us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 41.240s 2031.245us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 51.460s 1541.969us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 132.360s 5673.453us 1 1 100.00
flash_ctrl_write_word_sweep 7.410s 84.568us 1 1 100.00
flash_ctrl_read_word_sweep 6.860s 128.114us 1 1 100.00
flash_ctrl_ro 84.150s 7467.258us 1 1 100.00
flash_ctrl_rw 344.830s 7447.559us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 24.960s 856.776us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 647.530s 130258.369us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 62.080s 10064.650us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.710s 116.206us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.020s 18.217us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 10.290s 110.949us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 10.290s 110.949us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.230s 46.042us 1 1 100.00
flash_ctrl_csr_rw 9.810s 112.862us 1 1 100.00
flash_ctrl_csr_aliasing 43.550s 1508.287us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.880s 230.684us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.230s 46.042us 1 1 100.00
flash_ctrl_csr_rw 9.810s 112.862us 1 1 100.00
flash_ctrl_csr_aliasing 43.550s 1508.287us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.880s 230.684us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 45.610s 64.127us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 45.610s 64.127us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 45.610s 64.127us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 45.610s 64.127us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 29.930s 60.653us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1670.590s 2019.092us 1 1 100.00
flash_ctrl_tl_intg_err 207.740s 1756.313us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 207.740s 1756.313us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 207.740s 1756.313us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.690s 62.852us 1 1 100.00
flash_ctrl_wr_intg 6.780s 84.911us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 46.570s 66.287us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 59.010s 137.975us 1 1 100.00
flash_ctrl_disable 10.480s 73.396us 1 1 100.00
flash_ctrl_sec_info_access 40.620s 714.457us 1 1 100.00
flash_ctrl_connect 7.620s 70.073us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.500s 22.504us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.810s 112.862us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 45.610s 64.127us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.810s 112.862us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 45.610s 64.127us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.810s 112.862us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 45.610s 64.127us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.480s 73.396us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.690s 62.852us 1 1 100.00
flash_ctrl_access_after_disable 7.650s 59.880us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 17.300s 39.521us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.480s 73.396us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 18.980s 412.498us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 344.830s 7447.559us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 170.760s 7928.829us 1 1 100.00
flash_ctrl_rw_derr 159.310s 5262.887us 1 1 100.00
flash_ctrl_integrity 435.570s 9249.433us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1123.430s 171374.581us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1670.590s 2019.092us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1670.590s 2019.092us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1670.590s 2019.092us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1670.590s 2019.092us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.630s 754.422us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 6.020s 6.699us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.640s 100.134us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1670.590s 2019.092us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1670.590s 2019.092us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1670.590s 2019.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 22.080s 622.615us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 414.370s 513.354us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 1 test run
flash_ctrl_phy_host_grant_err 83636771929974884760225915805084718813986805950984392180591878688790654497255 125
UVM_ERROR @ 6698.8 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 6698.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---