Simulation Results: hmac

 
09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.00 %
  • code
  • 97.38 %
  • assert
  • 98.02 %
  • func
  • 44.61 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.51 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 11.020s 635.679us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.740s 15.215us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.780s 12.998us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.440s 6182.566us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.590s 184.909us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.440s 68.078us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.780s 12.998us 1 1 100.00
hmac_csr_aliasing 2.590s 184.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 26.760s 18291.759us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 31.290s 795.919us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.910s 251.030us 1 1 100.00
hmac_test_sha384_vectors 20.540s 2634.430us 1 1 100.00
hmac_test_sha512_vectors 19.860s 259.415us 1 1 100.00
hmac_test_hmac256_vectors 7.160s 950.060us 1 1 100.00
hmac_test_hmac384_vectors 8.140s 484.326us 1 1 100.00
hmac_test_hmac512_vectors 11.420s 6041.306us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 7.020s 9255.196us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 578.790s 4510.682us 1 1 100.00
error 1 1 100.00
hmac_error 40.200s 1037.346us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 34.330s 4167.864us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 11.020s 635.679us 1 1 100.00
hmac_long_msg 26.760s 18291.759us 1 1 100.00
hmac_back_pressure 31.290s 795.919us 1 1 100.00
hmac_datapath_stress 578.790s 4510.682us 1 1 100.00
hmac_burst_wr 7.020s 9255.196us 1 1 100.00
hmac_stress_all 171.200s 21186.374us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 11.020s 635.679us 1 1 100.00
hmac_long_msg 26.760s 18291.759us 1 1 100.00
hmac_back_pressure 31.290s 795.919us 1 1 100.00
hmac_datapath_stress 578.790s 4510.682us 1 1 100.00
hmac_wipe_secret 34.330s 4167.864us 1 1 100.00
hmac_test_sha256_vectors 8.910s 251.030us 1 1 100.00
hmac_test_sha384_vectors 20.540s 2634.430us 1 1 100.00
hmac_test_sha512_vectors 19.860s 259.415us 1 1 100.00
hmac_test_hmac256_vectors 7.160s 950.060us 1 1 100.00
hmac_test_hmac384_vectors 8.140s 484.326us 1 1 100.00
hmac_test_hmac512_vectors 11.420s 6041.306us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 11.020s 635.679us 1 1 100.00
hmac_long_msg 26.760s 18291.759us 1 1 100.00
hmac_back_pressure 31.290s 795.919us 1 1 100.00
hmac_datapath_stress 578.790s 4510.682us 1 1 100.00
hmac_burst_wr 7.020s 9255.196us 1 1 100.00
hmac_error 40.200s 1037.346us 1 1 100.00
hmac_wipe_secret 34.330s 4167.864us 1 1 100.00
hmac_test_sha256_vectors 8.910s 251.030us 1 1 100.00
hmac_test_sha384_vectors 20.540s 2634.430us 1 1 100.00
hmac_test_sha512_vectors 19.860s 259.415us 1 1 100.00
hmac_test_hmac256_vectors 7.160s 950.060us 1 1 100.00
hmac_test_hmac384_vectors 8.140s 484.326us 1 1 100.00
hmac_test_hmac512_vectors 11.420s 6041.306us 1 1 100.00
hmac_stress_all 171.200s 21186.374us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 171.200s 21186.374us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.600s 19.179us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.650s 17.651us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.130s 52.165us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.130s 52.165us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.740s 15.215us 1 1 100.00
hmac_csr_rw 0.780s 12.998us 1 1 100.00
hmac_csr_aliasing 2.590s 184.909us 1 1 100.00
hmac_same_csr_outstanding 2.050s 586.612us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.740s 15.215us 1 1 100.00
hmac_csr_rw 0.780s 12.998us 1 1 100.00
hmac_csr_aliasing 2.590s 184.909us 1 1 100.00
hmac_same_csr_outstanding 2.050s 586.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.740s 246.846us 1 1 100.00
hmac_tl_intg_err 3.550s 240.754us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.550s 240.754us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 11.020s 635.679us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 5.640s 147.534us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 163.320s 3575.818us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.390s 899.770us 1 1 100.00