Simulation Results

Simulation Results: i2c

09/06/2026 15:30:25 DVSim: v1.49.9 sha: 76f732e json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.67 %

code
81.42 %

assert
97.46 %

func
78.12 %

line
96.41 %

branch
92.33 %

cond
84.86 %

toggle
89.45 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	9.390s	1605.362us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	4.250s	533.012us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.810s	24.892us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.820s	58.028us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.810s	1271.115us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.480s	45.963us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.060s	29.479us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.820s	58.028us	1	1	100.00
	i2c_csr_aliasing	1.480s	45.963us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.810s	17.805us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	922.370s	23093.046us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	1606.580s	73521.026us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.790s	41.775us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	72.150s	5135.833us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	31.060s	2114.019us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.010s	89.699us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.930s	335.061us	1	1	100.00
	i2c_host_fifo_reset_rx	2.540s	637.317us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	97.190s	9067.112us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	4.840s	2283.787us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.250s	62.698us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.990s	491.810us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	116.140s	50885.529us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.550s	4067.388us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	11.400s	927.321us	1	1	100.00
	i2c_target_intr_smoke	6.020s	7553.904us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.930s	1326.609us	1	1	100.00
	i2c_target_fifo_reset_tx	1.550s	1040.375us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	18.330s	29504.413us	1	1	100.00
	i2c_target_stress_rd	11.400s	927.321us	1	1	100.00
	i2c_target_intr_stress_wr	19.150s	23837.420us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.530s	3762.527us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	3.850s	3054.701us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.710s	1306.548us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	10.850s	10234.591us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.770s	1461.826us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.620s	191.283us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	1606.580s	73521.026us	1	1	100.00
	i2c_host_perf_precise	1.320s	99.845us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	4.840s	2283.787us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.130s	110.534us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.110s	2342.565us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.970s	2300.292us	1	1	100.00
	i2c_target_nack_txstretch	1.960s	572.675us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	6.540s	228.104us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.670s	1642.039us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.660s	54.779us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.790s	49.164us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.540s	187.030us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.540s	187.030us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.810s	24.892us	1	1	100.00
	i2c_csr_rw	0.820s	58.028us	1	1	100.00
	i2c_csr_aliasing	1.480s	45.963us	1	1	100.00
	i2c_same_csr_outstanding	1.130s	58.815us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.810s	24.892us	1	1	100.00
	i2c_csr_rw	0.820s	58.028us	1	1	100.00
	i2c_csr_aliasing	1.480s	45.963us	1	1	100.00
	i2c_same_csr_outstanding	1.130s	58.815us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.560s	516.697us	1	1	100.00
	i2c_sec_cm	0.990s	134.452us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.560s	516.697us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	25.830s	1532.909us	1
target_error_intr				1
	i2c_target_unexp_stop	1.180s	146.373us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	0.820s	189.182us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	62621571031777328107905129019960058537925773995643710719391194577390199274035	80	UVM_INFO @ 17804921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	32769036382496576040252898522031458729446386202225183802484109238875513191366	85	UVM_INFO @ 189182037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_stress_all	2719890251425690442839919209559082514020227944825326096976895535099951405425	189	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @1094142
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	15508987085358605566763410786343472569486847077395378640749300689014965673360	84	UVM_INFO @ 491810349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	15877823414805585723390172351469397233425665347532721936586381330079356740632	78	UVM_INFO @ 146372909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	25332657275257741945781242056287902611808650192143736881721378969139795297131	79	UVM_INFO @ 10234591426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	110335733046144660756540572870177114935427381215134155081872064633502623919946	97	UVM_INFO @ 1532909442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	79134078656365402087783485771646489275885648156987143381676550690932006016551	87	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------